AM29BL802CB-65RZE Advanced Micro Devices, AM29BL802CB-65RZE Datasheet

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AM29BL802CB-65RZE

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AM29BL802CB-65RZE
Description
Manufacturer
Advanced Micro Devices
Datasheet

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Am29BL802C
Data Sheet
The following document contains information on Spansion memory products. Although the document
is marked with the name of the company that originally developed the specification, Spansion will
continue to offer these products to existing customers.
Continuity of Specifications
There is no change to this data sheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal data sheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these
products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Spansion memory solutions.
Publication Number 22371 Revision C
Amendment 7 Issue Date November 3, 2006

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AM29BL802CB-65RZE Summary of contents

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Data Sheet The following document contains information on Spansion memory products. Although the document is marked with the name of the company that originally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications ...

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THIS PAGE LEFT INTENTIONALLY BLANK. ...

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DATA SHEET Am29BL802C 8 Megabit (512 K x 16-Bit) CMOS 3.0 Volt-only Burst Mode Flash Memory DISTINCTIVE CHARACTERISTICS ■ 32 words sequential with wrap around (linear 32), bottom boot ■ One 8 Kword, two 4 Kword, one 48 Kword, three ...

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GENERAL DESCRIPTION The Am29BL802C Mbit, 3.0 Volt-only burst mode Flash memory devices organized as 524, 288 words. The device is offered in a 56-pin SSOP package. These devices are designed to be pro- grammed in-system with the ...

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TABLE OF CONTENTS This page left intentionally blank Product Selector Guide . . . . . . . . . . . . . . . . ...

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PRODUCT SELECTOR GUIDE Family Part Number Regulated Voltage Range: V Speed Option Temperature Range: Industrial (I), Extended (E) Max access time ACC Max CE# access time Max burst access time ...

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CONNECTION DIAGRAMS WE# RESET# RY/BY# A18 A17 CE OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 V SS CLK BAA# November 3, 2006 22371C7 ...

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PIN CONFIGURATION A0–A18 = 19 addresses DQ0–DQ15 = 16 data inputs/outputs CE# = Chip Enable Input. This signal shall be asynchronous relative to CLK for the burst mode. OE# = Output Enable Input. This signal shall be asynchronous relative to ...

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... Megabit (512 K x 16-Bit) CMOS High Performance Burst Mode Flash Memory 3.0 Volt-only Read, Program, and Erase Valid Combinations Am29BL802CB-65R ZI, ZE, ZF, ZK Am29BL802CB-70R ZI, ZE, ZF, ZK Am29BL802CB-90R ZI, ZE, ZF, ZK Am29BL802CB-120R ZI, ZE, ZF, ZK For information on full voltage range options (2.7–3.6 V), please contact AMD. November 3, 2006 22371C7 TEMPERATURE RANGE ° ...

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DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register it- self does not occupy any addressable memory loca- tion. The register is composed ...

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Requirements for Reading Array Data Array in Asynchronous (Non-Burst) Mode To read array data from the outputs, the system must drive the CE# and OE# pins control and selects the device. OE# is the output control and ...

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IND# End of Burst Indicator The IND# output signal goes low when the device is ouputting the last word of a 32-word burst sequence (word Da+31). When the starting address was loaded with LBA#, the 5-bit burst address counter was ...

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Embedded Algorithms). The system READY can read data t after the RESET# pin returns ...

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... V (11 12 address pin ID A9. Address pins A6, A1, and A0 must be as shown in Table 3. Am29BL802C Autoselect Codes (High Voltage Method) Description CE# Manufacturer ID: AMD L Device ID: Am29BL802CB L (Bottom Boot Block) Sector Protection Verification L Burst Mode Status Logic Low = Logic High = V IL Note: The autoselect codes may also be accessed in-system via command sequences. See Table 4. ...

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START PLSCNT = 1 RESET Wait 1 μs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...

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Temporary Sector Unprotect This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin During this mode, formerly protected ID sectors can ...

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See the “Reset Com- mand” section, next. See also “Requirements for Reading Array Data Array in Asynchronous (Non-Burst) Mode” in the “Key to Switch- ing Waveforms” section for more information. The Read Operations table ...

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Step CLK LBA# BAA# Data OE# Figure 4. Burst Mode Read with 25 MHz CLK Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits ...

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Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program- ming operation. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed ...

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The system can determine the status of the erase op- eration by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading ...

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Burst Mode. To enter Burst Mode either the Erase operation must be allowed to complete normally can be prematurely terminated by issuing a Hardware Reset. Burst Mode While in Burst Mode the Erase Suspend command ...

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Command Definitions Table 4. Am29BL802C Command Definitions Command Sequence (Note 1) Read (Note 6) Reset (Note 7) Manufacturer ID Device ID, Bottom Boot Block Sector Protect Verify (Note 9) Burst Mode Status (Note 10) Program Unlock Bypass Unlock Bypass Program ...

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WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 5 and the following subsections de- scribe the functions of these bits. DQ7, RY/BY#, and ...

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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since ...

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The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle ...

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Operation Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Reading within Erase Suspended Sector Erase Suspend Reading within Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C Ambient Temperature with Power Applied ...

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DC CHARACTERISTICS CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 (Notes ...

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DC CHARACTERISTICS (Continued) Zero Power Flash 500 1000 Note: Addresses are switching at 1 MHz Figure 11. I Current vs. Time (Showing Active and Automatic Sleep Currents) CC1 ...

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TEST CONDITIONS Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent Figure 13. Test Setup Key to Switching Waveforms WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V Input 0.0 V Figure 14. Input Waveforms ...

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AC CHARACTERISTICS Read Operations Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...

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AC CHARACTERISTICS Burst Mode Read Parameter JEDEC Std. Description Initial Access Time t LBA# Valid Clock to Output Delay IACC (See Note) Burst Access Time t BACC BAA# Valid Clock to Output Delay t LBA# Setup Time LBAS t LBA# ...

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AC CHARACTERISTICS Addresses CE# OE# WE# Outputs RESET# RY/BY Figure 15. Conventional Read Operations Timings CE# CLK t LBAS LBA# BAA# t ACS A0: A18 Aa t ACH DQ0: DQ15 OE#* IND# November 3, 2006 22371C7 D A ...

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AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded t READY Algorithms) to Read or Write (See Note) RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write (See Note) t RESET# ...

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AC CHARACTERISTICS Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH ...

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AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Note program address program data ...

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AC CHARACTERISTICS Erase Command Sequence (last two cycles Addresses 2AAh CE Data RY/BY# t VCS V CC Note sector address (for Sector Erase Valid Address for ...

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AC CHARACTERISTICS t RC Addresses VA t ACC OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last status read ...

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AC CHARACTERISTICS Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Figure 22. ...

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AC CHARACTERISTICS RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# Note: For sector protect For sector unprotect ...

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AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH ...

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AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written ...

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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Programming Time Chip Programming Time (Note 3) Notes: 1. Typical program and erase times assume the following conditions: 25 programming typicals assume checkerboard pattern. 2. Under worst case ...

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PHYSICAL DIMENSIONS* SSO056—56-Pin Shrink Small Outline Package Am29BL802C Dwg rev AB; 10/99 22371C7 November 3, 2006 ...

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REVISION SUMMARY Revision A (June 1, 1999) Initial release. Revision A+1 (June 25, 1999) General Description Corrected the device density in the first paragraph. Command Definitions Reading Array Data in Burst Mode: Added reference to Figure 3 in the first ...

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... Copyright © 1999–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...

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