CY7C335-66PC Cypress Semiconductor Corporation., CY7C335-66PC Datasheet
CY7C335-66PC
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CY7C335-66PC Summary of contents
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... The user-configurable macrocells enable the designer to des- ignate JK-, RS-, T-, or D-type devices so that the number of product terms required to implement the logic is minimized. The CY7C335 is available in a wide variety of packages in- cluding 28-pin, 300-mil plastic and ceramic DIPs, PLCCs, and LCCs. I ...
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... I C335–3 CY7C335–66 CY7C335–50 66.6 66.6 140 160 Function Output Enable Controlled by Product Term Output Enable Controlled by Pin 14 State Register Output is Fed Back to Input Array I/O Macrocell is Configured as an Input and Output of Input Path is Fed to Array ICLK1 Controls the Input Register I/O Macrocell ...
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... State Selects Data from I/O Macrocell Input Path of Macrocell A of Macrocell Pair 1—Programmed Selects Data from I/O Macrocell Input Path of Macrocell B of Macrocell Pair 1 INPUT INPUTREGISTER BYPASS INPUT CLOCK 1 MUX C6 Figure 1. CY7C335 Input Macrocell 3 CY7C335 Function TO ARRAY REG MUX C7 C335–4 ...
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... CLK 1 MUX SCLK2 RESET PRODUCT TERM 0 TO ARRAY FEED BACK MUX 1 C1 ICLK1 ICLK2 0 TO ARRAY SHARED INPUT MUX 1 FROM ADJACENT MACROCELL CX (11 – 16) Figure 2. CY7C335 Input/Output Macrocell C0 OUTPUT REG 1 BYPASS MUX OUTPUT PIN 14: OE ENABLE 0 MUX INPUT INPUT REGISTER REG ...
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... Figure 3. CY7C335 Hidden Macrocell SCLK2 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS PIN 1 1 ICLK1 ICLK2 MUX 0 C9 PIN 2 0 MUX 1 C8 PIN 3 1 MUX 0 C10 Figure 4. CY7C335 Input Clocking Scheme STATE Q CLK R MUX C5 C335–6 SCLK1 TO OUTPUT MACROCELLS AND HIDDEN MACROCELLS 1 MUX 0 1 MUX ...
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... V = Max GND CC IN Outputs Open V = Max., CC Outputs Disabled (in High Z State), Device Operating at f External (f MAX MAX5 Test Conditions MHz 2. MHz OUT 6 CY7C335 Ambient Temperature + 10% – + 10% – +125 C 5V 10% Min. Max. Com’l 2.4 Mil/Ind Com’l 0.5 Mil/Ind [3] 2.2 [3] 0.8 – ...
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... GND 3 ns OUTPUT =2.00V (d) Three-state Delay Load (Load2) Output Waveform Measurement Level V OH 0. 0. 0.5V Figure 5. Test Waveforms 7 CY7C335 ALL INPUT PULSES 90% 90% 10 C335–11 (b) R=125 (190 MIL C335– C335–12 C335–13 C335–14 C335–15 C335– ...
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... Output Data Stable from Input Clock Minus Input IOH IH 33x Register Hold Time for 7C335 t Pin 14 Enable to Output Enabled PZX t Pin 14 Disable to Output Disabled PXZ f Maximum Frequency of (2) CY7C335s in Input Reg- MAX1 istered Mode (Lowest of 1/(t [5] 1/( Maximum Frequency Data Path in Input Registered MAX2 ...
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... Delay (Through Logic Array) Notes: 6. This specification is intended to guarantee interface compatibility of the other members of the CY7C330 family with the CY7C335. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. 7. This part has been designed with the capability to reset during system power-up. Following power-up, the input and output registers will be reset to a logic LOW state ...
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... Output Data Clock Stable Time From Output Clock Minus OH2 IH Input Register Hold Time f Maximum Frequency with Internal Feedback in Output Reg- MAX3 [5] istered Mode f Maximum Frequency of (2) CY7C335s in Output Registered MAX4 Mode (Lower of 1/( Maximum Frequency Data Path in Output Registered Mode MAX5 (Lowest of 1/(t ), 1/( – ...
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... Switching Waveform INPUTOR I/O PIN t IS INPUT REG. CLOCK OUTPUT REG. CLOCK t IOH OUTPUT t PD PIN [7] Power-Up Reset Waveform 90 OUTPUT CLOCK COS t ICO t ICER PXZ t POR 11 CY7C335 ICEA t PZX C335–20 t COS t WL C335–21 ...
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... Block Diagram (Page SCLK1 1 (C9 (C6,7) (C8) (C10) 3 (C6,7) 4 (C6,7) 5 (C6,7) 6 (C6,7) 7 (C6,7) SCLK2 LOWER SECTION 12 CY7C335 64 RESET node= node= node= node= node=34 11 node=33 ...
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... Block Diagram (Page UPPER SECTION 9 (C4,5) 10 (C4,5) 11 (C4,5) 12 (C4,5) 13 (C4,5) 14 (C4, SET CY7C335 15 20 node= node=32 13 node= node= node= node=30 OE C335–23 ...
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... CY7C335–83LMB CY7C335–83QMB CY7C335–83WMB 140 CY7C335–83HC CY7C335–83JC CY7C335–83WC 66.6 160 CY7C335–66QMB 140 CY7C335–66HC CY7C335–66JC CY7C335–66PC CY7C335–66WC 50 140 CY7C335–50JC CY7C335–50PC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups ...
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... Package Diagrams 28-Lead (300-Mil) CerDIP D22 MIL-STD-1835 D–15 Config.A 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C–4 28-Lead Plastic Leaded Chip Carrier J64 28-Pin Windowed Leadless Chip Carrier Q64 MIL-STD-1835 C–4 15 CY7C335 ...
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... Package Diagrams (continued) 28-Pin Windowed Leaded Chip Carrier H64 16 CY7C335 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Windowed CerDIP W22 MIL-STD-1835 D– 15Config.A CY7C335 ...