LS7166 LSI Computer Systems, Inc., LS7166 Datasheet
LS7166
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LS7166 Summary of contents
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... The IC communicates with external circuits through an 8-bit three state I/O bus. Control and data words are written into the LS7166 through the bus. In addition to the I/O bus, there are a number of discrete inputs and out- puts to facilitate instantaneous hardware based control func- tions and instantaneous status indication ...
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PR (Preset register). The PR is the input port for the CNTR. The CNTR is loaded with a 24 bit data via the PR. The data is first written into the WRITE cycle sequence of Byte 0 ...
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TABLE 1 - Register Addressing Modes ...
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OCCR (Output Control Register) Initializes CNTR and output operating modes. Bit # (Quadrature Register). Selects quadrature count mode (See Fig. 7) Bit # ...
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I/O DESCRIPTION: (See REGISTER DESCRIPTION for I/O Prgramming.) Data-Bus (D0 - D7) (Pin 8 - Pin 15). The 8-line data bus is a three-state I/O bus for interfacing with the system bus. CS (Chip Select Input) (Pin 2). A logical ...
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TRANSIENT CHARACTERISTICS (See Timing Diagrams in Fig. 2 thru Fig 5.5V 0˚ to 85˚C, unless otherwise specified Parameter Clock A/B "Low” Clock A/B "High" Clock A/B Frequency (See NOTE 1) Clock ...
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LTCR CLK ( CLK (B) Q0 (Internal) Q1 (Internal) Q2-Q23 (Internal) CNTR=FFFFFD CNTR=FFFFFE CNTR=FFFFFF CNTR=000000 (PR=CNTR) COMP NOTE FIGURE 2 . LOAD COUNTER, UP CLOCK, DOWN CLOCK, COMPARE OUT, CARRY, BORROW ...
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T SRS CS C/D T CRS DATA BUS CS C/D WR DATA BUS LCTR DN CLK Q0 (INTERNAL) Q1 (INTERNAL) Q2-Q23 (INTERNAL) CNTR LD (INTERNAL) BW CNTR LOAD (LCTR or MCR BASED) UP CLK OR DN CLK ...
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A B UPCLK (x1) (Internal) DNCLK (x1) (Internal) UPCLK (x2) (Internal) DNCLK (x2) (Internal) UPCLK (x4) (Internal) DNCLK (x4) (Internal) UP/DN (OSR Bit 7166-110503-9 FORWARD CQV T CQV T CBW FIGURE 7. ...
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... INPUT) RD (WRITE INPUT (CONTROL /DATA INPUT) C/D 6 (COUNT INPUT (COUNT INPUT (AB GATE/LOAD LATCH) ABGT/RCTR (LOAD CTR/LOAD LATCH) LCTR/LLTC 3 PR/OL ADDRESS (+ (GND FIGURE 8. LS7166 BLOCK DIAGRAM 7166-110103-10 I BUFFER D0, D6, INPUT BUFFER AND DECODE LOGIC -D7 PR/OL ADDRESS CLOCK DN CLOCK D0 -D4 OSR QR OCCR ...
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... FIGURE 9. 80C31/8051 TO LS7166 INTERFACE IN EXTERNAL ADDRESS MODE 8051 80C31 AD0 P0.0 AD1 P0.1 AD2 P0.2 AD3 P0.3 AD4 P0.4 AD5 P0.5 AD6 P0.6 AD7 P0.7 ALE WR/ RD/ NOTE: Port_0 is open drain output. Add pull-up resistors to all Port_0 i/0 lines. 7166-110503-11 74HC573 ...
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... FIGURE 10. 8751 INTERFACE TO LS7166 IN I/O MODE UR 31 VCC P0.0 ER/VP P0.1 P0 P0.3 P0.4 18 P0.5 X2 P0.6 9 P0.7 RESET P2.0 12 INT0 P2.1 13 8051 P2.2 INT1 15 T0 P2.3 14 P2.4 T1 P2.5 P1.0 1 P1.0 P2.6 P1.1 2 P1.1 P2.7 P1.2 3 P1.2 P1.3 4 P1.3 RD P1.4 5 P1.4 WR P1.5 6 P1.5 PSEN P1 ...
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... PC0 31 PC1 PC1 32 PC2 PC2 33 PC3 PC3 34 PC4 PC4 35 PC5 PC5 36 PC6 PC6 37 PC7 PC7 38 42 PD0 43 PD1 44 PD2 45 PD3 46 PD4 PD5 47 MODA 25 MODB 68HC11A1 7166-110103-13 FIGURE 11. LS7166 TO 68HC11 INTERFACE U3 D0 PC0 PC1 PC2 PC3 PC4 ADDRESS D5 PC5 DECODE D6 PC6 PC7 ...
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... ISA BUS AEN IOR/ IOW/ 7166-110503-14 FIGURE 12. LS7166 INTERFACE EXAMPLE ADDRESS DECODER LS7166 IOW IOR C ...
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... FIGURE 13. 68000 INTERFACE TO LS7166 ADDRESS R/W LDS/UDS 68000 68008 68010 AS DTACK CLK CLOCK 7166-062306-15 DATA BUS LS373 DECODE S74 S74 C 7166 S74 CK R ...
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... C Sample Routines for Interfacing with LS7166 #include <stdio.h> #include <stdlib.h> #include <conio.h> #define DATAMODE(arg) (arg + 0) #define CTRLMODE(arg) (arg + 1) /************************************************************************/ /* MCR (Master Control Register Select MCR */ #define MCR(arg) (arg | 0x00) /* Master Reset */ /* Reset CNTR, ICR, OCCR, QR, BWT, CYT, OL, COMPT, and PR/OL Byte Pointer */ ...
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Decrement CNTR once for inputs are enabled */ #define Decr_CNTR 0x04 /* Increment CNTR once for inputs are enabled */ #define ...
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QR (Quadrature Register Select QR */ #define QR(arg) (arg | 0xC0) /* Enable x4 Quadrature Mode */ #define En_x4QM 0x03 /* Enable x2 Quadrature Mode */ #define En_x2QM 0x02 /* Enable x1 Quadrature Mode */ #define En_x1QM ...
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Write data into 7166 Preset Register Addr has address of 7266 counter Data has 24 bit data to be written to PR register */ void Write_7166_PR(int Addr, unsigned long Data); void Write_7166_PR(int Addr, unsigned long Data){ outp(CTRLMODE(Addr), MCR(Rst_BP)); outp(DATAMODE(Addr), ...