LS7266R1-S LSI Computer Systems, Inc., LS7266R1-S Datasheet
LS7266R1-S
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LS7266R1-S Summary of contents
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... DD SS • TTL/CMOS compatible I/Os. • LS7266R1 (DIP); LS7266R1-SD (Skinny DIP); LS7266R1-S (SOIC); LS7266R1-TS (TSSOP) LS7266R1 Registers: LS7266R1 has a set of registers associated with each X and Y axis. All X-axis registers have the name prefix X, whereas all Y-axis registers have the prefix Y. Selection of a specific register for Read/Write is made from the decode of the three most significant bits (D7-D5) of the data-bus ...
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Flag Register: XFLAG and YFLAG The FLAG registers hold the status information of the CNTRs and can be read out on the data bus. The E bit of a FLAG register is set to 1 when the noise pulses at ...
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Counter Mode Registers: XCMR and YCMR The CNTR operational mode is programmed by writing into the CMRs. 7 DEFINITIONS OF COUNT MODES: Range Limit. In range limit count mode, an upper and a lower limit is set, mimicking limit switches ...
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Input/Output Control Register: XIOR and YIOR The functional modes of the programmable input and output pins are written into the IORs. IOR Select IOR addressed by X/Y input 1: Select both XIOR ...
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C ...
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Transient Characteristics Parameter Symbol Read Cycle (See Fig Pulse Width CS Set-up Time CS Hold Time C/D Set-up Time C/D Hold Time X/Y Set-up Time X/Y Hold Time Data Bus Access Time Data Bus Release Time ...
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... D0-D7 Data Bus input/output. The 8-bit three-state data bus is the I/O port through which all data transfers (Pins 4-11) take place between the LS7266R1 and the host processor. FCK (Pin 2) Filter clock input in quadrature mode. The FCK is divided down internally by two 8-bit programmable prescalers, one for each channel. ...
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C C INPUT DATA t 1 FCK t 3 FCK n (Note ...
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A B INDEXI (Note 5) X1 CLOCK (Note 6) X2 CLOCK (Note 6) X4 CLOCK (Note 6) IDX (Note 7) Note 5: Shown here is positive index with solid line depicting 1/4 cycle index and dotted line depicting 1/2 cycle ...
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DOWN DIRECTION (B) COUNT IN (A) GATE (ABG) FIGURE 6. COUNT (A), DIRECTION (B) AND GATE (ABG) INPUTS IN NON-QUADRATURE MODE 999998 999999 CNTR RCNTR LCNTR FIGURE CNTR ...
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WRITE INPUT REG SBYTE2 8 8 PR2 (8) PR1 CNTR 24 24 COMPARATOR BYTE 0 BYTE 1 BYTE 2 SBYTE2 8 OL2 (8) 8 READ/WRITE I/O BUF DATA-BUS FIGURE 10. SINGLE-AXIS BLOCK DIAGRAM SHOWING MAJOR DATA ...
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... AT/XT AEN IOR IOW FIGURE 11A. LS7266R1 INTERFACE EXAMPLES R/W LDS DTACK FIGURE 11B. LS7266R1 INTERFACE EXAMPLES 7266R1-111196- ...
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... C Sample Routines for Interfacing with LS7266R1 #include<stdlib.h> #include <stdio.h> #include <conio.h> #define XDATA(arg) (arg +0) #define XCMD (arg) (arg + 1) #define YDATA (arg) (arg +2) #define YCMD (arg) (arg +3) // RLD Reg. #define RLD (arg) (arg | 0x80) #define XRLD (arg) (arg | 0) #define YRLD (arg) XRLD(arg) ...
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PR Reg. for Modulo N Counter to 0x123456 outp(XDATA(Addr),0x56); //Least significant Byte first outp(XDATA(Addr),0x34); //then middle byte outp(XDATA(Addr),0x12); //then most significant byte //Enable Counters outp(XCMD(Addr),IOR(EnAB)); } /* Write_7266_PR Input: Addr has Address of 7266 counter. Data: has 24 bit ...