AM79C961KC Advanced Micro Devices, AM79C961KC Datasheet
AM79C961KC
Specifications of AM79C961KC
Related parts for AM79C961KC
AM79C961KC Summary of contents
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... Bus Master Mode all transfers are performed using + This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended to help you to evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. ...
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AMD the integrated DMA controller. This configuration en- hances system performance + PCnet-ISA controller to bypass the platform DMA con- troller and directly address the full 24-bit memory space. The implementation of Bus Master Mode allows mini- mum parts count ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C961 K DEVICE NUMBER/DESCRIPTION Am79C961 Valid Combinations AM79C961 KC, KC ...
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AMD TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION RELATED PRODUCTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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BUS INTERFACE UNIT (BIU ...
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AMD TAP FSM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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CSR0: PCnet-ISA+ Controller Status Register CSR1: IADR[15: ...
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AMD CSR78: Transmit Ring Length CSR80: Burst and FIFO Threshold Control CSR82: Bus Activity Timer CSR84–85: DMA Address CSR86: Buffer Byte Counter CSR88–89: Chip ID . CSR92: Ring Length Conversion . CSR94: Transmit Time Domain Reflectometry Count CSR96–97: Bus Interface ...
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Bus Masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AMD BLOCK DIAGRAM: BUS MASTER MODE AEN DACK[3, 5-7] DRQ[3, 5-7] IOCHRDY IOCS16 IOR IOW ISA Bus IRQ[ 10, Interface 11, 12] MASTER MEMR MEMW REF RESET SBHE BALE SD[0-15] Buffer LA[17-23] Management SA[0-19] SLEEP SHFBUSY EEDO ...
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CONNECTION DIAGRAM: BUS MASTER DVSS3 1 MASTER 2 DRQ7 3 DRQ6 4 DRQ5 5 DVSS10 6 DACK7 7 DACK6 8 DACK5 9 LA17 10 LA18 11 LA19 12 LA20 13 DVSS4 14 LA21 15 LA22 16 LA23 17 SBHE 18 ...
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AMD PIN DESIGNATIONS: BUS MASTER Listed by Pin Number Pin # Name 1 DVSS3 MASTER 2 3 DRQ7 4 DRQ6 5 DRQ5 6 DVSS10 DACK7 7 DACK6 8 DACK5 9 10 LA17 11 LA18 12 LA19 13 LA20 14 DVSS4 ...
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PIN DESIGNATIONS: BUS MASTER Listed by Pin Name Name Pin # AEN 44 AVDD1 103 AVDD2 108 AVDD3 96 AVDD4 91 AVSS1 100 AVSS2 98 BALE 55 BPCS 126 CI- 106 CI+ 107 DACK3 62 DACK5 9 DACK6 8 DACK7 ...
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AMD PIN DESIGNATIONS: BUS MASTER Listed by Group Pin Name ISA Bus Interface AEN BALE DACK[3, 5-7] DRQ[3, 5-7] IOCHRDY IOCS16 IOR IOW IRQ[ 10, 11, 12, 15] LA[17-23] MASTER MEMR MEMW REF RESET SA[0-19] SBHE SD[0-15] ...
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PIN DESIGNATIONS: BUS MASTER (continued) Listed by Group Pin Name Attachment Unit Interface (AUI Twisted Pair Transceiver Interface (10BASE-T) RXD TXD TXPD IEEE 1149.1 Test Access Port Interface (JTAG) TCK TDI TDO TMS Power Supplies AVDD AVSS ...
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AMD PIN DESCRIPTION: BUS MASTER MODE These pins are part of the bus master mode. In order to understand the pin descriptions, definition of some terms from a draft of IEEE P996 are included. IEEE P996 Terminology Alternate Master: Any ...
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IRQ 10, 11, 12, 15 Interrupt Request An attention signal which indicates that one or more of the following status flags is set: BABL, MISS, MERR, RINT, IDON, RCVCCO, JAB, MPCO, or TXDATSTRT. All status flags ...
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AMD IRQ15/APCS Address PROM Chip Select When programmed as APCS in Plug and Play Register F0, this signal is asserted when the external Address PROM is read. When an I/O read operation is per- formed on the first 16 bytes ...
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BLOCK DIAGRAM: SHARED MEMORY MODE AEN IOCHRDY IOR IOW ISA Bus IRQ[ 10, Interface 11, 12] IOCS16 MEMR MEMW REF RESET SA[0-15] SBHE SD[0-15] Management SMA SLEEP BPAM SMAM SHFBUSY EEDO EEDI EESK EECS DVDD[1-7] DVSS[1-13] AVDD[1-4] ...
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AMD CONNECTION DIAGRAM: SHARED MEMORY DVSS3 1 SMA 2 SA0 3 SA1 4 SA2 5 DVSS10 6 SA3 7 SA4 8 SA5 9 SA6 10 SA7 11 SA8 12 SA9 13 DVSS4 14 SA10 15 SA11 16 SA12 17 SBHE ...
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PIN DESIGNATIONS: SHARED MEMORY Listed by Pin Number Pin # Name 1 DVSS3 SMA 2 3 SA0 4 SA1 5 SA2 6 DVSS10 7 SA3 8 SA4 9 SA5 10 SA6 11 SA7 12 SA8 13 SA9 14 DVSS4 15 ...
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AMD PIN DESIGNATIONS: SHARED MEMORY Listed by Pin Name Name Pin # AEN 44 AVDD1 103 AVDD2 108 AVDD3 96 AVDD4 91 AVSS1 100 AVSS2 98 BPAM 55 BPCS 126 CI- 106 CI+ 107 DI- 104 DI+ 105 DO- 101 ...
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PIN DESIGNATIONS: SHARED MEMORY Listed by Group Pin Name ISA Bus Interface AEN IOCHRDY IOCS16 IOR IOW IRQ[ 10, 11, 12, 15] MEMR MEMW REF RESET SA[0-15] SBHE SD[0-15] Board Interfaces IRQ15/APCS BPCS BPAM DXCVR/EAR LED0 LED1 ...
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AMD PIN DESIGNATIONS: SHARED MEMORY (continued) Listed by Group Pin Name Attachment Unit Interface (AUI Twisted Pair Transceiver Interface (10BASE–T) RXD TXD TXPD IEEE 1149.1 Test Access Port Interface (JTAG) TCK TDI TDO TMS Power Supplies AVDD ...
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PIN DESCRIPTION: SHARED MEMORY MODE ISA Interface AEN Address Enable This signal must be driven LOW when the bus performs an I/O access to the device. IOCHRDY I/O Channel Ready + When the PCnet-ISA controller is being accessed, a HIGH ...
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AMD BOARD INTERFACE APCS/IRQ15 Address PROM Chip Select This signal is asserted when the external Address PROM is read. When an I/O read operation is per- formed on the first 16 bytes in the PCnet-ISA controller’s I/O space, APCS is ...
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All outputs will be placed in their normal reset condition. + PCnet-ISA controller inputs will be ignored except for the SLEEP pin itself. Deassertion of SLEEP results in wake-up. The system must delay ...
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AMD PIN DESCRIPTION: NETWORK INTERFACES AUI CI+, CI– Control Input This is a differential input pair used to detect Collision (Signal Quality Error Signal). DI+, DI– Data In This is a differential receive data input pair to the PCnet- ISA+ ...
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FUNCTIONAL DESCRIPTION + The PCnet-ISA controller is a highly integrated system solution for the PC-AT ISA architecture. It provides an Ethernet controller, AUI port, and 10BASE-T trans- + ceiver. The PCnet-ISA controller can be directly interfaced to an ISA system ...
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AMD 16-Bit System Data SD[0-15] PCnet-ISA Controller ISA 24-Bit System Bus Address SA[0-19] LA[17-23] 1-504 BPCS PRDB[0-7] PRDB[2]/EEDO + PRDB[1]/EEDI PRDB[0]/EESK SHFBUSY EECS VCC Bus Master Block Diagram Plug ...
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SD[0-15] 16-Bit System Data PCnet-ISA SA[0-19] 24-Bit LA[17-23] System Address IRQ15/APCS IRQ12/FlashWE ISA Bus Plug and Play Compatible with Flash Support Shared Memory Mode System Interface The Shared Memory mode is the other fundamental op- erating mode available on the ...
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AMD selection: automatic selection, software selection, and jumper selection of AUI or 10BASE-T interface. In the automatic selection mode, the PCnet-ISA troller will select the interface that is connected to the network by checking the Link Status state machine. If ...
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SD[0-15] 16-Bit System Data PCnet-ISA Controller 24-Bit System Address SA[0-19] ISA SHFBUSY SRAM BPAM Bus VCC Plug and Play Compatible with Flash Memory Support PLUG AND PLAY Plug and Play is a standardized method of configuring jumperless adapter cards in ...
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AMD Isolate the Plug and Play card Read the cards resource data Identify the card Configure its resources The Plug and Play mode of operation allows the follow- ing benefits to the end user. Eliminates all jumpers or dip switches ...
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State Isolation Read from serial Get one bit from isolation register serial identifier Yes No ID bit = “1H” Leave SD in Drive “55H” high-impedance on SD[7:0] No Wait for next read from serial isolation register Drive “AAH” Leave SD ...
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AMD Cards must be assigned a CSN before they will respond to the other commands defined in the specification. It should be noted that the protocol permits the 8-bit checksum to be stored in non-volatile memory on the card or ...
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AND (CSN = 0) State Isolation Notes 1. CSN = Card Select Number 2. RESET or the Reset command causes a state transition from the cur- rent state to Wait for Key and sets all CSNs to ...
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AMD Address Port Value Name Set RD_DATA Port 0x00 Serial Isolation 0x01 Config Control 0x02 Wake[CSN] 0x03 Resource Data 0x04 Status 0x05 Card Select Number 0x06 Logical Device Number 0x07 Plug and Play Logical Device Configuration Registers + The PCnet-ISA ...
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Plug and Play Logical Device Control Registers Address Port Value Name Activate 0x30 For each logical device there is one activate register that controls whether or not the logical device is active on the ISA bus. Bit[0], if set, activates ...
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AMD Register Index Name Interrupt request level 0x70 select 0 Interrupt request type 0x71 select 0 Register Index Name DMA channel select 0 0x74 DETAILED FUNCTIONS EEPROM Interface The EEPROM supported by the PCnet-ISA an industry standard 93C56 2-Kbit EEPROM ...
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Serial EEPROM Byte Map The following is a byte map of the XXC56 series of + EEPROMs used by the PCnet-ISA IEEE Address (Bytes 0–5) EISA Config Reg. Internal Registers Plug and Play Reg. See Appendix C Note: Checksum is ...
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AMD Serial EEPROM Byte Map The following is a byte map of the XXC56 series of + EEPROMs used by the PCnet-ISA Word Location EISA Config Reg ...
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Plug and Play Register Map The following chart and its bit descriptions show the in- ternal configuration registers associated with the Plug Plug and Play Register Bit 7 Bit 6 0x00 0x01 0x02 0 0 0x03 0x04 0x05 0 0 ...
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AMD The following chart and its bit descriptions show the in- ternal command registers associated with the Plug and Plug and Play Register Bit 7 Bit 6 0x60 0 0 0x61 IOAM2 IOAM1 0x70 0 0 0x71 0 0 0x74 ...
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DMA[2:0] DMA Channel 0x74). Controls the DRQ and DMA selection of PCnet-ISA The DMA[2:0] register will be written with a value from the EEPROM. Mode Only} The DRQ signal will not be driven unless EE_VALID is set or Non-EEPROM sequen- ...
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AMD selection will respond as an 8-bit port. AEN_CS External Decode Logic for I/O Registers. When written with a one, the PCnet-ISA AEN pin as I/O chip select bar, to allow for external decode logic for the upper address bit ...
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Use Without EEPROM In some designs, especially PC motherboard applica- tions, it may be desirable to eliminate the EEPROM altogether. This would save money, space, and power consumption. The operation of this mode is similar to when the + PCnet-ISA ...
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AMD Once the BIU has been granted bus mastership, it will perform four data transfer cycles (eight bytes) before re- linquishing the bus. The four transfers within the mastership period will always be read cycles to contiguous addresses. There are ...
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However, the ring lengths can be manually defined (up to 65535) by writing the transmit and receive ring length registers (CSR76,78) directly. Each ring entry contains the following information: The address of the actual message ...
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AMD 24-Bit Base Address Pointer to Initialization Block CSR2 CSR1 IADR[23:16] IADR[15:0] RES Initialization Block MODE PADR[15:0] PADR[31:16] PADRF[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RLEN RES RDRA[23:16] TDRA[15:0] TLEN RES TDRA[23:16] Polling When there is no channel activity and there ...
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TMD1 and TMD0 of the current TDTE at periodic polling intervals. All information collected during polling activity will be stored internally in the appropriate CSRs. (i.e. CSR18–19, CSR40, CSR20–21, CSR42, CSR50, CSR52). Unowned descriptor status will be internally ignored. A ...
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AMD + PCnet-ISA controller in the transmit descriptor ring and therefore, the condition is treated as a fatal error. To avoid this situation, the system should always set the transmit chain descriptor own bits in reverse order the ...
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OWN bit of RMD1 when the first buffer is full. Receive data transfers to the second buffer may occur before the PCnet-ISA ler ...
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AMD Addressing (source and destination address handling) The first 6 bytes of information after SFD will be inter- preted as the destination address field. The MAC engine provides facilities for physical, logical, and broadcast address reception. In addition, multiple physical ...
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The IEEE 802.3 Standard also allows optional two part deferral after a receive message. See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.1: “Note : It is possible for the PLS carrier sense indication to fail to be asserted during a collision on ...
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AMD required, the MORE bit will be set. If all 16 attempts ex- perienced collisions, the RTRY bit (in TMD2) will be set (ONE and MORE will be clear), and the transmit mes- sage will be flushed from the FIFO. ...
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Internal Transmit Enable (ITXEN). The in- ternal transmit clock is also used as a stable bit-rate clock by the receive section of the MENDEC and con- troller. The oscillator requires an external 0.005% crystal external 0.01% ...
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AMD Carrier Tracking and End of Message The carrier detection circuit monitors the DI inputs after IRXCRS is asserted for an end of message. IRXCRS de-asserts bit times after the last positive transi- tion on the incoming ...
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Twisted Pair Transmit Function The differential driver circuitry in the TXD and TXP pins provides the necessary electrical driving capability and the pre-distortion control for transmitting signals over maximum length Twisted Pair cable, as specified by the 10BASE-T supplement to ...
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AMD On receipt of the first packet with valid ETD following re- set or link fail, the T-MAU will use the inferred polarity information to configure its RXD input, regardless of its previous state. On receipt of a second packet ...
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To allow simple serial to parallel conversion, SF/BD is provided as a strobe and/or marker to indicate the de- lineation of bytes, subsequent to the SFD. This provides a mechanism to allow not only capture and/or decoding of the physical ...
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AMD General Purpose Serial Interface (GPSI) + The PCnet-ISA controller contains a General Purpose Serial Interface (GPSI) designed for testing the digital portions of the chip. The MENDEC, AUI, and twisted pair interface are by-passed once the device is set ...
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IEEE 1149.1 Test Access Port Interface An IEEE 1149.1 compatible boundary scan Test Access Port is provided for board-level continuity test and diag- nostics. All digital input, output, and input/output pins are tested. Analog pins, including the AUI differential driver ...
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AMD Power Saving Modes + The PCnet-ISA controller supports two hardware power-savings modes. Both are entered by asserting the SLEEP pin LOW coma mode, the PCnet-ISA controller will go into deep sleep with no support to automatically wake ...
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All accesses to 8-bit resources (which do not return MEMCS16 or IOCS16) use SD0- odd byte is ac- cessed, the Current Master swap buffer turns on. During an odd byte read the swap buffer copies the data from ...
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AMD arbitrates for the Private Data Bus (PRDB) if necessary. IOCHRDY is driven LOW during accesses to the ad- dress PROM. When the Private Data Bus becomes available, the controller drives APCS active, releases + PCnet-ISA IOCHRDY, turns on the ...
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The following signals are not driven by the Permanent Master and are simply pulled HIGH: BALE, IOCHRDY, IOCS16, MEMCS16, SRDY. Therefore, the PCnet-ISA controller assumes the memory which it is accessing is 16 bits wide and can complete an access ...
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AMD maintained until IOR goes inactive, at which time the access cycle ends. Data is removed from SD0-7 within 30 ns. + The PCnet-ISA controller will perform 8-bit ISA bus cy- cle operation for all resources (registers, PROMs, SRAM) if ...
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The PCnet-ISA controller assumes 16-bit ISA memory bus cycles for the SRAM, so this same logic must assert MEMCS16 to the ISA bus if 16-bit bus cycles are to be supported. A 16-bit SRAM bus cycle begins with the ...
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AMD Non-negative setup and hold times for address and data with respect to SRWE are guaranteed. SRWE has a pulse width of typically 100 ns, minimum 75 ns. Transmit Operation The transmit operation and features of the PCnet-ISA controller are ...
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The PCnet-ISA+ controller will ensure that collisions which occur within 512 bit times from the start of trans- mission (including preamble) will be automatically retried with no host intervention. The ...
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AMD All receive frames can be accepted by setting the PROM bit in CSR15. When PROM is set, the PCnet-ISA troller will attempt to receive all messages, subject to minimum frame enforcement. Promiscuous mode over- rides the effect of the ...
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Normal events which may occur and which are handled + autonomously by the PCnet-ISA cally collisions within the slot time and automatic runt + packet ...
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AMD Since a 10BASE-T hub does not normally feed the sta- tion’s transmitter outputs back into the station’s receiver inputs, the use of external loopback in a 10BASE-T sys- tem usually requires some sort of external hardware that connects the ...
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PCnet-ISA CONTROLLER REGISTERS + The PCnet-ISA controller implements all LANCE (Am7990) registers, plus a number of additional regis- + ters. The PCnet-ISA controller registers are compatible with the original LANCE, but there are some places where previously reserved LANCE ...
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AMD MERR assertion will set the ERR bit. MERR is set by the Bus Interface Unit and cleared by writing a “1”. Writing a “0” has no effect. MERR is cleared by RESET or by setting the STOP bit. 10 ...
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STOP STOP assertion disables the chip from all external activity. The chip remains inactive until either STRT or INIT are set. If STOP, STRT and INIT are all set to- gether, STOP will override STRT and INIT. STOP is ...
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AMD 5 LAPPEN Look Ahead Packet Processing (LAPPEN) . When set to a one, the LAPPEN bit will cause the + PCnet-ISA ate an interrupt following the descriptor write operation to the first buffer of a receive packet. This interrupt ...
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In order to set ENTST, it must be written with a “1” during the first write access to CSR4 after RESET. Once a “0” is written to this bit location, ENTST cannot be set ...
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AMD The JAB bit can be reset even if the jabber condition is still present. JAB is set by the TMAU circuit and cleared by writing a “1”. Writ- ing a “0” has no effect. JAB is also cleared by ...
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CSR13: Physical Address Register, PADR[31:16] Bit Name Description 15-0 PADR[31:16] Physical Address PADR[31:16]. Undefined until in- itialized either automatically by loading the initialization block or directly by an I/O write to this register. The PADR bits are transmitted PADR[0] first ...
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AMD Read/write accessible only when STOP bit is set. Cleared by RESET. TSEL Transmit Mode Select. TSEL controls the levels at which the AUI drivers rest when the AUI transmit port is idle. When TSEL = 0, DO+ and DO- ...
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LOOP INTL MENDECL Loopback Mode Non-loopback External Loopback Internal Loopback Include MENDEC Internal Loopback Exclude MENDEC Read/write accessible only when STOP bit is set. LOOP is cleared by ...
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AMD CSR26-27: Next Receive Descriptor Address Bit Name Description 31-24 RES Reserved locations. Written as zero and read as undefined. 23-0 NRDA Contains the next RDRE address pointer. Read/write accessible only when STOP bit is set. CSR28-29: Current Receive Descriptor ...
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Read/write accessible only when STOP bit is set. CSR44-45: Next Receive Status and Byte Count Bit Name Description 31-24 NRST Next Receive Status. This field is a copy of bits 15:8 of RMD1 of the next receive descriptor. Read/write accessible ...
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AMD CSR56-57: Temporary Storage Bit Name Description 31-0 TMP4 Temporary Storage location. Read/write accessible only when STOP bit is set. CSR58-59: Temporary Storage Bit Name Description 31-0 TMP5 Temporary Storage location. Read/write accessible only when STOP bit is set. CSR60-61: ...
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CSR72: Receive Ring Counter Bit Name Description 15-0 RCVRC Receive Ring Counter location. Contains a Two’s complement binary number used to number the current receive descriptor. This counter interprets the value in CSR76 as pointing to the first descriptor; a ...
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AMD write its data until at least 64 bytes (or the entire frame if <64 bytes) have been transmitted onto the network. This ensures that for collisions within the slot time window, transmit data need not be re-written to the ...
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Register by issuing increment commands to increment the memory address for sequential operations. The DMABA register is undefined + PCnet-ISA operation. This register has meaning only if the PCnet-ISA Bus Master Mode. Read/write accessible only when STOP bit is set. ...
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AMD 32-bit or 16-bit internal write op- erations are performed. This register is used internally by the BIU/BMU as a word or byte swapper. The swap register can perform 32-bit operations that the PC can not; the register is ex- ...
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All registers are 16 bits. The “Default” value is the value in the register after reset and is hexadecimal. Refer to the section “LEDs” for information on LED control logic. ISACSR MNEMONIC Default 0 MSRDA 0005H 1 ...
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AMD access method to Plug and Play registers will occur. Default is zero. 8 APWEN Address PROM Write Enable reset to zero by RESET. When asserted, this pin allows write ac- cess to the internal Address PROM RAM. ...
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PCnet-ISA , performing self con- figuration. This command must be last write to ISACSR3 Regis- ter. PCnet-ISA to any slave commands while loading the EE_PROM register. EE_LOAD will be reset with a zero after EE_PROM is read. It takes ...
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AMD 0 disables the signal, 1 enables the signal. 3 RVPOL E Enable Receive Polarity Signal. Enables LED pin assertion when receive polarity is correct on the 10BASE-T port. Clearing the bit indicates this function ignored. 2 ...
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ISACSR7: LED3 Status Bit Name Description ISACSR7 controls the func- tion(s) that displays. Multiple functions can be simultaneously enabled on this LED pin. The LED display will indicate the logical OR of the enabled functions. ISACSR7 de- faults to Transmit ...
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AMD R/TLEN 000 001 010 011 100 101 110 111 If a value other than those listed in the above table is de- sired, CSR76 and CSR78 can be written after initialization is complete. See the description of the ap- ...
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Received Message Destination Address MATCH = 1: Packet Accepted MATCH = 0: Packet Rejected Receive Descriptors The Receive Descriptor Ring Entries (RDREs) are com- posed of four receive message fields (RMD0-3). Together they contain the following information: ...
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AMD If a Buffer Error occurs, an Over- flow Error may also occur internally in the FIFO, but will not be reported in the descriptor status entry unless both BUFF and OFLO errors occur at the same time. BUFF is ...
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PCnet-ISA was a reserved bit in the LANCE (Am7990). 12 MORE MORE indicates that more than one re-try was needed to trans- mit a frame. MORE is written by the PCnet-ISA bit has ...
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AMD reached. Upon UFLO error, the transmitter is turned off (CSR0, TXON = 0). UFLO is written by the PCnet-ISA 13 RES RESERVED bit. The PCnet- ISA+ controller will write this bit with a “0”. 12 LCOL LATE COLLISION indicates ...
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Register Summary Ethernet Controller Registers (Accessed via RDP Port) RAP Addr Symbol 00 CSR0 01 CSR1 02 CSR2 03 CSR3 04 CSR4 05 CSR5 06 CSR6 07 CSR7 08 CSR8 09 CSR9 10 CSR10 11 CSR11 12 CSR12 13 CSR13 ...
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AMD Register Summary Ethernet Controller Registers (Accessed via RDP Port) (continued) RAP Addr Symbol 64-65 CSR64 66-67 CSR66 68-69 CSR68 70-71 CSR70 72 CSR72 74 CSR74 76 CSR76 78 CSR78 80 CSR80 82 CSR82 84-85 CSR84 86 CSR86 88-89 CSR88 ...
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Register Summary ISACSR—ISA Bus Configuration Registers (Accessed via IDP Port) RAP Addr Mnemonic 0 MSRDA 1 MSWRA LED0 5 LED1 6 LED2 7 LED3 8 SC *This value can be 0000H for systems that do ...
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AMD SYSTEM APPLICATION ISA Bus Interface Compatibility Considerations Although 8 MHz is now widely accepted as the standard speed at which to run the ISA bus, many machines have been built which operate at higher speeds with non- standard timing. ...
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SD[0-15] 16-Bit System Data PCnet-ISA Controller SA[0-19] 24-Bit LA[17-23] System Address IRQ15/APCS IRQ12/FlashWE ISA Bus Plug and Play Compatible with Flash Support BPCS PRDB[0-7] PRDB[0]/EESK + PRDB[1]/EEDI PRDB[2]/EEDO EECS ...
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AMD SD[0-15] 16-Bit System Data SA[0-15] 24-Bit System Address SMAM SHFBUSY ISA BPAM Bus VCC 1-580 BPCS PRAB(0:15) PRDB[0-7] PCnet-ISA+ Controller PRDB[2]/EEDO PRDB[1]/EEDI PRDB[0]/EESK EECS SROE SRWE Shared Memory ...
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SD[0-15] 16-Bit System Data PCnet-ISA Controller 24-Bit System Address SA[0-19] ISA SHFBUSY SRAM BPAM Bus VCC Plug and Play Compatible with Flash Memory Support PRAB[0-15] PRDB[0-7] BPCS SROE + ...
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AMD Optional Address PROM Interface The suggested address PROM is the Am27LS19, a 32x8 device. APCS should be connected directly to the device’s G input. A4–A0 27LS19 PROM G Q7–Q0 18183B-23 Address PROM Example Boot PROM Interface ...
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Interface The diagram below shows the proper 10BASE-T net- work interface design. Refer to the PCnet Family TXD+ TXP+ + TXD- PCnet-ISA PCnet-ISA Controller TXP- RXD+ RXD- Note: All resistors are 1% Note : All resistors ±1% 10BASE-T External ...
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AMD ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . ...
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DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description Attachment Unit Interface (continued) I Transmit Differential AODOFF Output Idle Current V Transmit Output Common CMT Mode Voltage V DO Transmit Differential ODI Output Voltage Imbalance ...
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AMD DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description Twisted Pair Interface (continued) V RXD Switching Threshold RXDTH V TXD and TXP Output TXH HIGH Voltage V TXD and TXP Output TXL LOW Voltage ...
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SWITCHING CHARACTERISTICS: BUS MASTER MODE Parameter Symbol Parameter Description Input/Output Write Timing AEN, SBHE, SA0–9 Setup t IOW1 IOW to AEN, SBHE,SA0–9 Hold t IOW2 IOW After IOW Assertion t IOW3 IOW Inactive t IOW4 IOW t SD Setup to ...
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AMD SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued) Parameter Symbol Parameter Description Master Mode Bus Release t Command Deassert to MMBR1 DACK t DRQ to MMBR2 MASTER t DRQ to MMBR3 DRQ to Command, SBHE, t MMBR4 SA0–19, LA17–23 Tristated Master ...
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SWITCHING CHARACTERISTICS: BUS MASTER MODE (continued) Parameter Symbol Parameter Description Master Mode Address PROM Read IOR to APCS t MA1 APCS Active t MA2 APCS t PRDB Setup to MA3 APCS t PRDB Hold After MA4 APCS to t IOCHRDY ...
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AMD SWITCHING CHARACTERISTICS: BUS MASTER MODE—FLASH READ CYCLE Parameter Symbol Parameter Description t REF, SBHE,SA0–19 Setup MFR1 MEMR to t REF, SBHE,SA0–19 Hold From MFR2 MEMR IOCHRDY to MEMR t MFR3 MEMR Inactive t MFR4 MEMR to BPCS t MFR5 ...
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SWITCHING CHARACTERISTICS: SHARED MEMORY MODE Parameter Symbol Parameter Description Input/Output Write Timing AEN, SBHE, SA0–9 Setup t IOW1 IOW to AEN, SBHE,SA0–9 Hold t IOW2 IOW From IOW Assertion t IOW3 IOW Inactive t IOW4 IOW t SD Setup to ...
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AMD SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued) Parameter Symbol Parameter Description Memory Read Timing SA0–15, SBHE, SMAM/BPAM t MR1 MEMR Setup to SA0–15, SBHE, SMAM/BPAM t MR2 MEMR Hold From MEMR Inactive t MR3 MEMR t SD Hold From MR4 ...
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SWITCHING CHARACTERISTICS: SHARED MEMORY MODE (continued) Parameter Symbol Parameter Description SRAM Read/Write, Boot PROM Read, Address PROM Read on Private Bus (continued) t PRDB Setup to PRAB PR8 Change, APROM Access t PRDB Hold After PRAB PR9 Change, APROM Access ...
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AMD SWITCHING CHARACTERISTICS: SHARED MEMORY MODE—FLASH READ CYCLE Parameter Symbol Parameter Description t BPAM, REF, SBHE, SA0–19 MFR1 MEMR Setup to t BPAM, REF, SBHE, SA0–19 Hold MFR2 MEMR From MEMR t IOCHRDY to MFR3 MEMR Inactive t MFR4 MEMR ...
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SWITCHING CHARACTERISTICS: EADI Parameter Symbol Parameter Description t SRD Setup to SRDCLK EAD1 t SRD Hold to SRDCLK EAD2 SF/BD Change to t SRDCLK EAD3 EAR Deassertion to t EAD4 SRDCLK (First Rising Edge) EAR Assertion From SFD t EAD5 ...
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AMD SWITCHING CHARACTERISTICS: GPSI Parameter Symbol Parameter Description Transmit Timing t STDCLK Period (802.3 Compliant) GPT1 t STDCLK HIGH Time GPT2 t TXDAT and TXEN Delay from GPT3 t RXCRS Setup to GPT4 t RXCRS Hold From GPT5 t CLSN ...
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SWITCHING CHARACTERISTICS: AUI Parameter Symbol Parameter Description AUI Port t DO+,DO- Rise Time (10% to 90%) DOTR t DO+,DO- Fall Time (90% to 10%) DOTF t DO+,DO- Rise and fall Time Mismatch DORM t DO+/- End of Transmission DOETD t ...
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AMD SWITCHING CHARACTERISTICS: 10BASE-T INTERFACE Parameter Symbol Parameter Description Transmit Timing t Transmit Start of Idle TETD t Transmitter Rise Time TR t Transmitter Fall Time TF t Transmitter Rise and Fall TM Time Mismatch t Idle Signal Period PERLP ...
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KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS Must be Steady May Change from May Change from Don’t Care, Any Change Permitted Does Not Apply ...
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AMD SWITCHING TEST CIRCUITS Sense Point DO+ DO– 1-600 18183B-26 Normal and Three-State Outputs AV DD 52.3 Test Point 154 100 pF AV ...
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SWITCHING TEST CIRCUITS TXD+ TXD– Includes Test Jig Capacitance TXP+ TXP– Includes Test Jig Capacitance 294 Test Point 294 100 18183B-28 TXD Switching Test ...
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AMD SWITCHING WAVEFORMS: BUS MASTER MODE AEN, SBHE, SA0–9 IOW SD AEN, SBHE, SA0–9 IOW IOCHRDY SD 1-602 Stable t IOW1 t IOW3 t IOW5 I/O Write without Wait ...
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SWITCHING WAVEFORMS: BUS MASTER MODE EESK (PRDB0) EECS EEDI (PRDB1) EEDO (PRDB2) SHFBUSY EESK (PRDB0) EECS EEDI (PRDB1) SHFBSY EED0 (PRDB2 ...
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AMD SWITCHING WAVEFORMS: BUS MASTER MODE EED0 (PRDB2) IOR IOCHRDY IOW EESK, EEDI, EECS, SHFBUSY AEN, SBHE, SA0–9 IOR SD 1-604 SL1 t SL2 Slave Serial EEPROM Latency ...
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SWITCHING WAVEFORMS: BUS MASTER MODE AEN, SBHE, SA0–9 IOR IOCHRDY SD IOW, MEMW MEMR, IOR Stable t IOR1 t t IOR6 IOR7 t IOR8 I/O Read with Wait States ...
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AMD SWITCHING WAVEFORMS: BUS MASTER MODE AEN, SBHE, SA0–9 IOCS16 REF DRQ t DACK t MMA3 MASTER MEMR/MEMW SBHE, SA0–19, LA17–23 1-606 IOCS1 IOCS16 Timings t MMA1 MMA2 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE DRQ DACK MASTER MEMR/MEMW SBHE, SA0–19, LA17–23 (Non Wait) SBHE, SA0–19, LA17–23 t MMW1 MEMW IOCHRDY t MMW10 SD0– MMBR1 MMBR2 t ...
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AMD SWITCHING WAVEFORMS: BUS MASTER MODE (Non Wait) SBHE, SA0–19, LA17–23 t MMR1 MEMR IOCHRDY SD0–15 AEN, SBHE, SA0–9 IOR IOCHRDY APCS (IRQ15) PRDB0–7 SD0–7 1-608 MMR5 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE BALE LA20–23 t MB13 REF, SBHE, SA0–19 t MB1 MEMR t MB14 IOCHRDY BPCS PRDB0–7 SD0– MB12 Stable Stable t MB3 t MB5 ...
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AMD SWITCHING WAVEFORMS: BUS MASTER MODE BALE LA20–23 t MFR13 REF, SBHE, SA0–19 t MFR1 MEMR t MFR14 IOCHRDY BPCS PRDB0–7 SD0–7 1-610 MFR12 Stable Stable t MFR3 ...
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SWITCHING WAVEFORMS: BUS MASTER MODE BALE LA20–23 t MFW14 SBHE, SA0–19 t MFW1 MEMW t t MFW15 IOCHRDY SD0-7 FL_WE (IRQ12) PRDB0 MFW13 Stable Stable MFW3 t MFW7 ...
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AMD SWITCHING WAVEFORMS: SHARED MEMORY MODE AEN, SBHE, SA0–9 IOW SD AEN, SBHE, SA0–9 t IOW IOCHRDY SD 1-612 Stable t t IOW1 IOW3 I/O Write without Wait States ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE AEN, SBHE, SA0–9 IOR SD AEN, SBHE, SA0–9 IOR IOCHRDY Stable t IOR1 t IOR5 Stable I/O Read without Wait States Stable t ...
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AMD SWITCHING WAVEFORMS: SHARED MEMORY MODE SA0–15, SBHE SMAM MEMW SD SA0–15, SBHE SMAM t MEMW IOCHRDY SD 1-614 Stable t t MW1 MW3 Memory Write without Wait States ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE SA0–15, SBHE SMAM MEMR SD SA0–15, SBHE SMAM/BPAM MEMR IOCHRDY Stable t MR1 t MR5 Stable Memory Read without Wait States Stable t ...
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AMD SWITCHING WAVEFORMS: SHARED MEMORY MODE IOW, MEMW MEMR, IOR AEN, SBHE, SA0–9 IOCS16 1-616 IOM1 I/O to Memory Command Inactive Time t IOCS1 IOCS16 Timings Am79C961 t ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE SBHE, SA0–15, BPAM t SFW1 MEMW IOCHRDY SD0-7 SRWE BPCS PRDB0 Stable t SFW3 t SFW7 t t SFW10 SFW11 t SFW9 Stable Flash ...
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AMD SWITCHING WAVEFORMS: SHARED MEMORY MODE REF, SBHE SA0-15 t SFR1 MEMR IOCHRDY SROE BPCS PRDB0–7 SD0–7 1-618 Stable t SFR3 t SFR5 t SFR6 t SFR8 Flash Read ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE PRAB SRWE PRDB SRCS (IRQ12) SRAM Write on Private Bus (When FL_Sel is Enabled) PRAB SROE PRDB SRCS (IRQ12) SRAM Read on Private Bus (When FL_Sel is Enabled ...
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AMD SWITCHING WAVEFORMS: SHARED MEMORY MODE PRAB BPCS PRDB PRAB0–9 APCS (IRQ15) PRDB 1-620 PR10 t t PR11 PR12 Boot PROM Read on Private Bus t PR7 Address ...
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SWITCHING WAVEFORMS: SHARED MEMORY MODE PRAB0 t PR14 SRWE PRDB FLCS PRAB0 FLOE FLCS PRDB PR17 t PR14 t t PR18 Flash Write on Private Bus t ...
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AMD SWITCHING WAVEFORMS: GPSI (First Bit Preamble) tGPT1 tGPT2 Transmit Clock (STDCLK) tGPT3 Transmit Data (TXDAT) tGPT3 Transmit Enable (TXEN) Carrier Present (RXCRS) (Note 1) Collision (CLSN) (Note 2) Notes RXCRS is not present during transmission, LCAR bit ...
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SWITCHING WAVEFORMS: EADI SRDCLK (LED3) One Zero One SRD (LED2) t EAD1 t EAD2 SF/BD (LED1) t EAD4 EAR (MAUSEL) SWITCHING WAVEFORMS: JTAG (IEEE 1149.1) INTERFACE TCK t t JTG3 JTG4 TDI t JTG5 TMS TDO ...
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AMD SWITCHING WAVEFORMS: AUI XTAL1 t XI ISTDCLK (Note 1) ITXEN (Note 1) 1 ITXDAT+ (Note 1) DO+ DO– DO Note: 1. Internal signal and is shown for clarification only. XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ ...
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SWITCHING WAVEFORMS: AUI XTAL1 ISTDCLK (Note 1) ITXEN (Note ITXDAT+ (Note 1) DO+ DO– Bit (n–2) Note: 1. Internal signal and is shown for clarification only. Transmit Timing—End of Packet (Last Bit = 1) P ...
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AMD SWITCHING WAVEFORMS: AUI DI+/– V ASQ t PWKDI t PWODI CI+/– V ASQ t PWOCI DO+/– 1-626 Receive Timing Diagram t PWKCI Collision Timing Diagram t DOETD 40 ...
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SWITCHING WAVEFORMS: 10BASE-T INTERFACE TXD+ TXP+ TXD– TXP– XMT t PWPLP TXD+ TXP+ TXD– TXP– t PWLP Transmit Timing t PERLP Idle Link Test Pulse ...
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AMD SWITCHING WAVEFORMS: 10BASE-T INTERFACE RXD Receive Thresholds (LRT = 0 in CSR15 bit 9) RXD Receive Thresholds (LRT = 1 in CSR15 bit 9) 1-628 Am79C961 V TSQ+ ...
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APPENDIX A + PCnet-ISA Compatible Media Interface Modules + PCnet-ISA COMPATIBLE 10BASE-T FILTERS AND TRANSFORMERS The table below provides a sample list of PCnet-ISA compatible 10BASE-T filter and transformer modules Manufacturer Part No. Bel Fuse A556-2006-DE 16-pin 0.3” DIL Bel ...
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AMD + PCnet-ISA Compatible DC/DC Converters The table below provides a sample list of PCnet-ISA compatible DC/DC converters available from various Manufacturer Part No. Halo Electronics DCU0-0509D Halo Electronics DCU0-0509E PCA Electronics EPC1007P PCA Electronics EPC1054P PCA Electronics EPC1078 Valor ...
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APPENDIX B Layout Recommendations for Reducing Noise DECOUPLING LOW-PASS R/C FILTER DESIGN + The PCnet-ISA controller is an integrated, single-chip Ethernet controller, which contains both digital and ana- log circuitry. The analog circuitry contains a high speed Phase-Locked Loop (PLL) ...
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AMD 6.8 F VDD Plane AVDD2 Pin 108 AVSS2 Pin PCnet-ISA To determine the value for the resistor and capacitor, the formula is Where ohms ...
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APPENDIX C Sample Configuration File SAMPLE CONFIGURATION FILE The following is a sample configuration file for the + PCnet-ISA device used in an AMD Ethernet card. This card requires one DMA channel, one interrupt, one I/O port in the 0x200-0x3FF ...
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AMD ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; Logical Device ID ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; DB 0x15 DB 0x11 DB 0x11 DB 0x22 DB 0x22 DB 0x01 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; I/O Port Descriptor ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; DB 0x47 DB 0x00 DB 0x00 DB 0x02 DB 0xE0 DB 0x03 DB 0x20 DB ...
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APPENDIX D Alternative Method for Initialization + The PCnet-ISA controller may be initialized by perform- ing I/O writes only. That is, data can be written directly to the appropriate control and status registers (CSR) instead of reading from the Initialization ...
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APPENDIX E Introduction of the Look Ahead Packet Processing (LAPP) Concept + A driver for the PCnet-ISA controller would normally require that the CPU copy receive frame data from the controller’s buffer space to the application’s buffer space after the ...
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SETUP: The driver should set up descriptors in groups of 3, with the OWN and STP bits of each set of three descriptors to read as follows: 11b, 10b, 00b. An option bit (LAPPEN) exists in CSR3, bit position 5. ...
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AMD operation is interleaved with the C7 and C8 operations. + C8: The PCnet-ISA controller will perform data DMA to the last buffer, whose pointer is pointing to appli- cation space. Data entering the last buffer will not need the ...
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LAPP Enable Software Requirements Software needs to set up a receive ring with descriptors formed into groups of 3. The first descriptor of each group should have OWN = 1 and STP = 1, the second descriptor of each group ...
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AMD The controller will discard all descriptors with OWN = 1 and STP = 0 and move to the next descriptor when searching for a place to begin a new frame . It dis- cards these desciptors by simply changing ...
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Assume that instead of the expected 1060 byte frame, a 900 byte frame arrives, either because there was an error in the network, or because this is the last frame in a file transmission sequence. Before the Descriptor Frame ...
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AMD 3) Assume that instead of the expected 1060 byte frame, a 100 byte frame arrives, because there was an error in the network, or because this is the last frame in a file transmission sequence, or per- haps because ...
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S5 and S7 as such: While the driver is polling for each descriptor, it could count the number of poll opera- tions performed and then adjust the number 1 buffer ...
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AMD Ethernet Ethernet Wire Controller activity: C10: ERP interrupt } is generated. C9: Controller writes descriptor #3. C8: Controller is performing intermittent bursts of DMA to fill data buffer #3. N2: EOM C7: Controller writes descriptor #2. C6: "Last chance" ...
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Descriptor OWN = 0 #9 SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE) Descriptor OWN = 1 #8 SIZE = S1+S2+S3+S4 Descriptor OWN = 1 #7 SIZE = HEADER_SIZE (minimum 64 bytes) Descriptor OWN = 0 #6 SIZE = 1518 - (S1+S2+S3+S4+HEADER_SIZE) Descriptor ...
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APPENDIX F Some Characteristics of the XXC56 Serial EEPROMs SWITCHING CHARACTERISTICS of a TYPICAL XXC56 SERIAL EEPROM INTERFACE Applicable over recommended operating range from TA = –40∞C to +85∞C, VCC = +1 +5 TTL ...
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VIH CS VIL VIH SK VIL VIH DI VIL VOH DO (READ) VOL VOH DO (PROGRAM) VOL Note: 1. This is the minimum SK period. ( tCSS tSKH tSKL tDIS tDIH tPDO tSV Status Valid Typical XXC56 Series ...