CY7B9950AI Cypress Semiconductor Corporation., CY7B9950AI Datasheet

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CY7B9950AI

Manufacturer Part Number
CY7B9950AI
Description
2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7B9950AI

Case
QFP-32L

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Cypress Semiconductor Corporation
Document #: 38-07338 Rev. *B
Features
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 100 ps
• Cycle-cycle jitter < 100 ps
• ± 2% max output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50 terminated lines
• LVCMOS/LVTTL over-voltage-tolerant reference input
• Phase adjustments in 625-/1250-ps steps up to +7.5 ns
• 2x, 4x multiply and (1/2)x, (1/4)x divide ratios
• Spread-Spectrum-compatible
• Industrial temp. range: –40 C to +85 C
• 32-pin TQFP package
Block Diagram
2F1:0
3F1:0
4F1:0
1F1:0
REF
FB
TEST
3
3
3
3
3
3
3
3
3
PE/HD
PLL
Phase
Phase
Select
Select
and /K
and /M
Phase
Select
Phase
Select
3
2.5/3.3V, 200-MHz High-Speed Multi-Phase
FS
3
VDDQ4
3901 North First Street
VDDQ1
sOE#
VDDQ3
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
4Q0
4Q1
Description
The CY7B9950 RoboClock
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to feedback input to achieve
different reference frequency multiplication and divide ratios
and zero input-output delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
Pin Configuration
VDDQ4
PE/HD
VSS
4Q0
3F1
4F1
4Q1
4F0
San Jose
1
2
3
4
5
6
7
8
CY7B9950
,
CA 95134
PLL Clock Buffer
is a low-voltage, low-power,
Revised March 4, 2003
RoboClock
24
23
22
21
20
19
18
17
CY7B9950
408-943-2600
1F1
1F0
sOE#
VDDQ1
1Q0
1Q1
VSS
VSS

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CY7B9950AI Summary of contents

Page 1

Features • 2.5V or 3.3V operation • Split output bank power supplies • Output frequency range: 6 MHz to 200 MHz • Output-output skew < 100 ps • Cycle-cycle jitter < 100 ps • ± 2% max output duty cycle ...

Page 2

Pin Description [1] Pin Name I/O 29 REF I LVTTL/LVCMOS TEST I Three-level 22 sOE Two-level 4 PE/ Three-level 24, 23, 26, nF[1:0] I Three-level 25 ...

Page 3

Table 4. MF Calculation which t NOM Table 5. Output Skew Settings nF[1:0] Skew (1Q[0:1],2Q[0:1]) [ addition to determining whether ...

Page 4

Absolute Maximum Conditions Parameter Description V Operating Voltage DD V Operating Voltage DD V Input Voltage IN(MIN) V Input Voltage IN(MAX) T Temperature, Storage S T Temperature, Operating Ambient A T Temperature, Junction J Ø Dissipation, Junction to Case JC ...

Page 5

DC Specifications @ 3.3V Parameter Description V 3.3 Operating Voltage DD V Input LOW Voltage IL V Input HIGH Voltage IH [9] V Input HIGH Voltage IHH [9] V Input MID Voltage IMM [9] V Input LOW Voltage ILL I ...

Page 6

AC Input Specifications Parameter Description T ,T Input Rise/Fall Time Input Clock Pulse PWC T Input Duty Cycle DCIN F Reference Input Frequency REF Switching Characteristics Parameter Description F Output Frequency Range OR VCO VCO Lock Range ...

Page 7

... REF OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Ordering Information Part Number CY7B9950AC 32 TQFP CY7B9950ACT 32 TQFP – Tape and Reel CY7B9950AI 32 TQFP CY7B9950AIT 32 TQFP – Tape and Reel Document #: 38-07338 Rev REF t PWL t t 0DCV 0DCV t t SKEWPR SKEWPR t SKEW0,1 ...

Page 8

Package Drawing and Dimension 32-lead Thin Plastic Quad Flatpack 1.0 mm A32 RoboClock is a registered trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. ...

Page 9

Document History Page Document Title: RoboClock CY7B9950 2.5/3.3V, 200-MHz High-Speed Multi-Phase PLL Clock Buffer Document Number: 38-07338 Rev. ECN No. Issue Date ** 121663 11/25/02 *A 122548 12/12/02 *B 124646 03/05/03 Document #: 38-07338 Rev. *B Orig. of Change RGL ...

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