LU3X54FT Agere Systems, LU3X54FT Datasheet

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LU3X54FT

Manufacturer Part Number
LU3X54FT
Description
QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/FX
Manufacturer
Agere Systems
Datasheet

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* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
Introduction
The LU3X54FT is a four-channel, single-chip com-
plete transceiver designed specifically for dual-speed
10Base-T, 100Base-TX, and 100Base-FX repeaters
and switches. It supports simultaneous operation in
three separate IEEE standard modes: 10Base-T,
100Base-TX, and 100Base-FX.
Each channel implements:
The LU3X54FT supports operations over two pairs of
unshielded twisted-pair (UTP) cable (10Base-T and
100Base-TX), and over fiber-optic cable (100Base-
FX).
It has been designed with a flexible system interface
that allows configuration for optimum performance
and effortless design. The individual per-port inter-
face can be configured as 100 Mbits/s MII, 10 Mbits/s
MII, 7-pin 10 Mbits/s serial, or bused mode.
Features
10 Mbits/s Transceiver
July 2000
QUAD-FET (Fast Ethernet Transceiver) for 10Base-T/100Base-TX/ FX
10Base-T transceiver function of IEEE 802.3.
Physical coding sublayer (PCS) of IEEE 802.3u.
Physical medium attachment (PMA) of IEEE
802.3u.
Autonegotiation of IEEE 802.3u.
MII management of IEEE 802.3u.
Physical medium dependent (PMD) of IEEE 802.3.
Compatible with IEEE * 802.3 10Base-T standard
for twisted-pair cable
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
100 Mbits/s TX Transceiver
Autopolarity detection and correction
Adjustable squelch level for extended line length
capability (two levels)
Interfaces with IEEE 802.3u media independent
interface (MII) or a serial 10 Mbits/s 7-pin interface
On-chip filtering eliminates the need for external
filters
Half- and full-duplex operations
Compatible with IEEE 802.3u MII (clause 22), PCS
(clause 23), PMA (clause 24), autonegotiation
(clause 28), and PMD (clause 25) specifications
Scrambler/descrambler bypass
Encoder/decoder bypass
3-statable MII in 100 Mbits/s mode
Selectable carrier sense signal generation (CRS)
asserted during either transmission or reception in
half duplex (CRS asserted during reception only in
full duplex)
Selectable MII or 5-bit code group interface
Full- or half-duplex operations
Optional carrier integrity monitor (CIM)
On-chip filtering and adaptive equalization that
eliminates the need for external filters
LU3X54FT

Related parts for LU3X54FT

LU3X54FT Summary of contents

Page 1

... Autonegotiation of IEEE 802.3u. MII management of IEEE 802.3u. Physical medium dependent (PMD) of IEEE 802.3. The LU3X54FT supports operations over two pairs of unshielded twisted-pair (UTP) cable (10Base-T and 100Base-TX), and over fiber-optic cable (100Base- FX). It has been designed with a flexible system interface that allows configuration for optimum performance and effortless design ...

Page 2

... Outline Diagram ......................................................................................................................................................52 208-Pin SQFP...................................................................................................................................................... 52 Tables Table 1. LU3X54FT Crystal Specifications .............................................................................................................. 6 Table 2 . LU3X54FT Pin Maps............................................................................................................................... 15 Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports) ................................................. 16 Table 4. MII/Serial Interface Pins in Bused MII Mode ............................................................................................ 18 Table 5. MII Management Pins .............................................................................................................................. 22 Table 6. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins....................................................................................... 22 Table 7 ...

Page 3

... Figure 4. Typical Single-Channel Fiber-Optic Interface ..........................................................................................10 Figure 5. Smart 10/100 Mbits/s Bused MII Mode...................................................................................................11 Figure 6. Separate 10/100 Mbits/s Bused MII Mode ..............................................................................................12 Figure 7. LU3X54FT Pinout for Normal MII Mode..................................................................................................13 Figure 8. LU3X54FT Pinout for Bused MII Mode ...................................................................................................14 Figure 9. Thermal Characteristics ..........................................................................................................................42 Figure 10. MDIO Input Timing ................................................................................................................................43 Figure 11. MDIO Output Timing .............................................................................................................................43 Figure 12 ...

Page 4

... SQFP or 208-pin SQFPH Single 5 V power supply Description Bused MII Mode The LU3X54FT has been designed for operation in two basic system interface modes of operation: Normal MII Mode (Four Separate MII Ports). The separate mode provides four independent RJ-45 to MII ports and is similar to having four independent 10/100 transceivers ...

Page 5

... The 20 MHz clock can be internally synthesized from the 25 MHz clock. The 25 MHz clock can also be internally generated by an on-chip oscillator if an external crystal is sup- plied. The LU3X54FT will automatically detect MHz clock is supplied crystal is being used to gener- ate the 25 MHz clock. LU3X54FT 5 ...

Page 6

... Series Resistance < Mode Each individual port of the LU3X54FT can be operated in 100Base-FX mode by selecting it through the pin program option (RXLED[D:A]/FX_MODE_EN[D:A], or through the register bit (register 29, bit 0). FX mode can operate in full or half duplex. Each individual chan- nel’s duplex can be set by register zero bit eight (0.8) or all ports duplex can be hardware configured at power up or rest by pin 201 FULL_DUP ...

Page 7

... Mbits/s TRANSCEIVER DRIVER AND FILTERS MANAGEMENT PMA PCS AUTONEGOTIATION 10 Mbits/s TRANSCEIVER DRIVER AND FILTERS MANAGEMENT PMA PCS AUTONEGOTIATION 10 Mbits/s TRANSCEIVER DRIVER AND FILTERS Figure 1. LU3X54FT Device Overview LU3X54FT FX_MODE_EN TX PMD/ FX PORT DRIVER AND FILTERS MUX FX_MODE_EN TX PMD/ FX PORT DRIVER AND FILTERS MUX ...

Page 8

... TX_CLK 10 Mbits/s TRANSCEIVER TX_EN TXD[0] CLK20 MDC MDIO MANAGEMENT 25 MHz LSCLK 125 MHz DPLL MHz Z 25 MHz CRYSTAL Figure 2. LU3X54FT Single-Channel Detail Functions 8 (continued) 100 Mbits/s TRANSCEIVER FAR-END SCRAMBLER FAULT GEN SD RX STATE MACHINE COLLISION SD DETECT CAR_STAT CARRIER DETECT RXERR_ST ALIGNER ...

Page 9

... July 2000 Description (continued) Application Diagrams Single-Channel Twisted-Pair Interface TPOUT+ LU3X54FT TPOUT– TPIN+ TPIN– MHz Figure 3. Typical Single-Channel Twisted-Pair (TP) Interface Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX V DDO 1:1 50 220 50 220 75 0. 1:1 0.01 F 0.01 F LU3X54FT RJ- 0. 0.01 F 0.01 F 5-5433(F).r9 9 ...

Page 10

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Description (continued) Application Diagrams (continued) Single-Channel Fiber-Optic Interface TPOUT+ LU3X54FT TPOUT– FOSD TPIN+ TPIN– MHz Figure 4. Typical Single-Channel Fiber-Optic Interface 10 V DDA V DDO 50 220 82 50 220 0.01 F 130 Data Sheet July 2000 0. 0. TDN SD RD ...

Page 11

... RX_CLK10 RX_CLK10 RXD_10 RXD_10 TX_CLK10 TX_CLK10 TXD_10 TXD_10 CRS_10/100 4 CRS_100 RX_EN10/100 4 RX_EN100 TX_EN10/100 4 TX_EN100 COL_10/100 4 COL_100 SECURITY10/100 4 TX_EN10/SECURITY TX_CLK25 TX_CLK25 TXD_100[3:0] TXD_100[3:0] TX_ER TX_ER RX_CLK25 RX_CLK25 RXD_100[3:0] RXD_100[3:0] RX_DV RX_DV RX_ER RX_ER MDC MDC MDIO MDIO SMART_MODE_SELECT BUSED_MII_MODE LU3X54FT LU3X54FT 5-5599.br2 11 ...

Page 12

... RX_EN10 4 RX_EN10 TX_EN10 4 TX_EN10 CRS_100 4 CRS_100 TX_EN100 4 TX_EN100 TX_CLK25 TX_CLK25 TXD_100[3:0] TXD_100[3:0] TX_ER TX_ER RX_CLK25 RX_CLK25 RXD_100[3:0] RXD_100[3:0] RX_DV RX_DV RX_ER RX_ER COL_100 4 COL_100 RX_EN100 4 RX_EN100 MDC MDC MDIO MDIO SMART_MODE_SELECT BUSED_MII_MODE Data Sheet July 2000 LU3X54FT 5-5599.ar5 Lucent Technologies Inc. ...

Page 13

... TPOUT–/FOOUT–[B] 47 VDDO 48 GNDO 49 TPOUT+/FOOUT+[A] 50 TPOUT–/FOOUT–[A] 51 VDDO 52 Figure 7. LU3X54FT Pinout for Normal MII Mode Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX LU3X54FT LU3X54FT VSS 156 RXD[0][B] 155 RX_CLK[B] 154 RX_ER[B]/RXD[4][B] 153 VDD ...

Page 14

... GNDO 45 POUT+/FOOUT+[B] 46 POUT–/FOOUT–[B] 47 VDDO 48 GNDO 49 POUT+/FOOUT+[A] 50 POUT–/FOOUT–[A] 51 VDDO 52 Figure 8. LU3X54FT Pinout for Bused MII Mode 14 LU3X54FT Data Sheet July 2000 VSS 156 RXD_10 155 RX_CLK10 154 NC 153 VDD 152 NC ...

Page 15

... Data Sheet July 2000 Pin Information (continued) Pin Maps Table 2. LU3X54FT Pin Maps Normal Mode Pins Bused Mode Pins RXD[D][3:0] CRS_10[D:A] CRS[D:A] CRS_100[D:A] TXD[C][3:0] RX_EN10[D:A] MII_EN[D:A] RX_EN100[D:A] TXD[3:0][D] TX_EN10[D:A] TX_EN[D:A] TX_EN100[D:A] RXD[3:0][C] COL_10[D:A] COL[D:A] COL_100[D:A] SPEEDLED[C] SMART_MODE_SELECT SPEEDLED[B] BUSED_MII_MODE ...

Page 16

... Pin Descriptions This section describes the LU3X54FT signal pins. Note that any register bit referenced includes the register num- ber and bit position. For example, register bit [29.8] is register 29, bit 8. Table 3. MII/Serial Interface Pins in Normal MII Mode (Four Separate MII Ports) ...

Page 17

... Transmit Data[4]. When the encoder/decoder bypass bit is set, this input serves as the TXD[4] input. When in 10 Mbits/s mode and SERIAL_SEL is active-high, this pin is ignored. I MII Enable. For normal MII mode of operation (nonbused mode), MII_EN for each channel must be tied high to enable each individual port being used. LU3X54FT Description 17 ...

Page 18

... When CRS_SEL is high, CRS_10 is asserted on receive activity only. CRS_SEL is set via the MII management interface or the CRS_SEL pin. When SMART_MODE_SELECT is asserted, the LU3X54FT will internally OR together the CRS_10 and the CRS_100 signals and output them on the CRS_100 signals. ...

Page 19

... O Shared Receive Data Valid. When this pin is driven high, it indicates that the LU3X54FT is recovering and decoding valid nibbles on RXD[3:0] and that the data is synchronous with RX_CLK. RX_DV is synchronous with RX_CLK. This pin is not used in serial 10 Mbits/s mode. ...

Page 20

... Security for 10/100 Mbits/s Smart Mode. When SMART_MODE_SELECT is enabled, these pins are redefined to be the security input pins for both 10 Mbits/s and 100 Mbits/s. When security is activated, the LU3X54FT will ignore the transmit data, and a fixed pattern is transmitted (all 1s for 10Base-T, alternating 1, 0 for 100TX) ...

Page 21

... Table 4. MII/Serial Interface Pins in Bused MII Mode (continued) Pin Signal 101 103 104 140 142 143 145 151 153 157 158 159 Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX Type O No Connect. Do not connect these pins Connect. These inputs should be grounded. LU3X54FT Description 21 ...

Page 22

... LU3X54FT and the station management. Control information is driven by the station management synchronous with MDC. Status information is driven by the LU3X54FT synchronous with MDC. This pin requires an external 1.5 k pull-up resistor. Maskable Status Interrupt. This pin will go high whenever there is a change in status as defined in Table 22 ...

Page 23

... For normal operating conditions, pull this pin low. I Band Gap Reference. Connect these pins ground. The parasitic load capacitance should be less than 15 pF. I Current Set 10 Mbits/s. An external resistor (22 placed from this pin to ground to set the 10 Mbits/s TP driver transmit output level. LU3X54FT Description 10% capacitor to 1% resistor 23 ...

Page 24

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Pin Information (continued) Pin Descriptions (continued) Table 7. Miscellaneous Pins (continued) Pin Signal 43 ISET_100 114 REF10 27 CLK20 166 TXLED[D]/ CARIN_EN 165 TXLED[C]/ ENC_DEC_BYPASS 164 TXLED[B]/ SCRAM_DESC_BYPASS 162 TXLED[A]/ REF_SEL 24 Type I Current Set 100 Mbits/s. An external resistor (nominally 24 placed from this pin to ground to set the 100 Mbits/s TP driver transmit output level ...

Page 25

... This input and the register bit [30.0] are ORed together. This pin has an internal 50 k pull-down resistor to set the default to normal link pulse ON mode. LU3X54FT Description pull-down resistors. pull-down resistors but not resistor, it will set PHYADD[2] ...

Page 26

... COL_10 and COL_100 signals will be output on the COL_100 pins. I/O Speed LED[B]. This pin indicates the operating speed of port B on the LU3X54FT. A high on this pin indicates 100 Mbits/s operation. A low indicates 10 Mbits/s operation. External buffers are necessary to drive the LEDs. ...

Page 27

... LU3X54FT will powerup or reset to the isolate mode. (MII outputs to high-impedance state.) This pin is internally pulled low through resistor. The default state is for the LU3X54FT to powerup or reset in a nonisolate mode. This pin and register bit [10.0] are ORed together during powerup and reset. ...

Page 28

... Type I Full Chip Reset. Reset must be asserted high for at least five LSCLK cycles. The LU3X54FT will come out of reset after 400 s. LSCLK must remain running during reset. I/O Half-Duplex LED[B]. When this output is high, it indicates half-duplex mode. When it is low, it indicates full duplex. External buffers are nec- essary to drive the LEDs ...

Page 29

... MDIO during a read transaction. During a write to the LU3X54FT, these bits are driven the station. During a read, the MDIO is not driven during the first bit time and is driven the LU3X54FT during the second bit time. ...

Page 30

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX MII Station Management Management Registers (MR) Register Overview The MII management 16-bit register (MR) set is implemented as described in the table below. Table 10. MII Management Registers (MR) Register Symbol Address 0 MR0 1 MR1 MR4 5 MR5 5 MR5 6 MR6 7 MR7 8—27 MR8—MR27 28 MR28 29 MR29 ...

Page 31

... This bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. The default state This bit is ORed with the H_DUPLED[D] pin during powerup or reset. Collision Test. When this bit is set the LU3X54FT will assert the COL signal in response to TX_EN. This bit should only be set when in loopback mode. ...

Page 32

... R Reserved. All bits will read 1.6 (NO_PA_OK) R Suppress Preamble. This bit is set indicating that the LU3X54FT accepts management frames with the preamble suppressed. 1.5 (NWAYDONE) R Autonegotiation Complete. When this bit indicates the autonegotia- tion process has been completed. The contents of registers MR4, MR5, MR6, and MR7 are now valid ...

Page 33

... This will allow the exchange of additional data. Data is carried by optional next pages of information. Acknowledge. This bit is the acknowledge bit from the link code word. Remote Fault. When set to 1, the LU3X54FT indicates to the link partner a remote fault condition. Reserved. These bits will read 0. ...

Page 34

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX MII Station Management Management Registers (MR) Table 15. MR5—Autonegotiation Link Partner (LP) Ability Register (Base Page) Bit Descriptions 1 Register/Bit Type 5.15 (LP_NEXT_PAGE) R 5.14 (LP_ACK) R 5.13 (LP_REM_FAULT) R 5.12:5 R (LP_TECH_ABILITY) 5.4:0 (LP_SELECT Note that the format for the bit descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters ...

Page 35

... Next Page Able. This bit is set to 1, indicating that this device supports the next-page function. Page Received. When this bit is set indicates that a NEXT_PAGE has been received. Link Partner Autonegotiation Capable. When this bit is set indicates that the link partner is autonegotiation capable. Description LU3X54FT Description 35 ...

Page 36

... LU3X54FT has detected and corrected a polarity reversal on the twisted pair. If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside the LU3X54FT. This bit is not valid in 100 Mbits/s operation. This bit defaults to 0. Disconnect. If this bit indicates a disconnect. This bit will latch high until read ...

Page 37

... Packet Error Indication Enable. When this bit packet error code, which indicates that the scrambler is not locked, will be reported on RXD[3:0] of the LU3X54FT when RX_ER is asserted on the MII. When this bit will disable this function. Default state is 0. Pulse Stretching. When this bit is set to 1, the COLED[D:A], TXLED[D:A], and RXLED[D:A] output signal will be stretched between approximately 42 ms— ...

Page 38

... REF10 is used for phase alignment. Default state is 0. Serial Select. When this bit is set Mbits/s serial mode will be selected. When the LU3X54FT is in 100 Mbits/s mode, this bit will be ignored. This bit is ORed with the H_DUPLED[C] pin during powerup and reset. ...

Page 39

... R Link Partner Pause. When this bit is set indicates that the LU3X54FT wishes to exchange flow control information. 31.9 (SPEED100) R Link Speed ...

Page 40

... MII Station Management Unmanaged Operations The LU3X54FT allows the user to set some of the station management functions during powerup or reset by strap- ping outputs high or low through weak resistors ( Table 23 shows the functions and their associated output pin. For detailed information on the function of these output pins, refer to the section on management registers described earlier in this data sheet ...

Page 41

... All Ports 100 Mbits/s FX All Ports 10 Mbits/s All Ports Autonegotiating * Typical power dissipations are specified at 5.0 V and 25 °C. This is the power dissipated by the LU3X54FT. An additional 0 power is required for the external twisted-pair driver termination resistors. Electrical Characteristics The following specifications apply for V Table 27 ...

Page 42

... QUAD-FET for 10Base-T/100Base-TX/FX Package and Thermal Characteristics The LU3X54FT is packaged in a 208-pin SQFP , plain plastic package (LU3X54FT-S208) or with an internal heat spreader (LU3X54FT-HS208). Both packages have identical dimensions and conform to the outline diagram in this data sheet. The heat spreader package provides enhanced thermal performance with a lower Theta-JC and Theta-JA ...

Page 43

... Note: MDIO turnaround (TA) time is a 2-bit time spacing between the register address field, and the data field of a frame to avoid drive conten- tion on MDIO during a read transaction. During a write to the LU3X54FT, these bits are driven the station. During a read, the MDIO is not driven during the first bit time and is driven the LU3X54FT during the second bit time. ...

Page 44

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Timing Characteristics (Preliminary) Table 30. MII Data Timing (25 pF Load) Name t1 RXD[3:0], RX_ER, RX_DV Valid to RX_CLK High t2 RX_CLK High to RXD[3:0], RX_DV, RX_ER Invalid t3 RX_CLK High t4 RX_CLK Low t5 RX_CLK Period t6 TX_CLK High t7 TX_CLK Low t8 TX_CLK Period t9 TXD, TX_EN, TX_ER, Setup to TX_CLK ...

Page 45

... Data Sheet July 2000 Timing Characteristics (Preliminary) RX_CLK RXD[3:0] RX_DV RX_ER Figure 13. MII Timing Requirements for LU3X54FT Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX (continued TX_CLK t7 TXD[3:0] TX_EN TX_ER t9 LSCLK TXD[3:0] TX_EN TX_ER t11 1st BIT OF J TPIN COL t13 LU3X54FT t6 t10 ...

Page 46

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Timing Characteristics (Preliminary) Table 31. Serial 10 Mbits/s Timing for TPIN, CRS, and RX_CLK Name t15 TPIN Activity to CRS Assertion t16 TPIN Activity to RX_CLK Valid t17 IDL to CRS Deassertion t18 Dead Signal to CRS Deassertion (RECEIVE—START OF PACKET) TPIN CRS RX_CLK Figure 14 ...

Page 47

... Time to Assert COL; LU3X54FT Is Transmitting; Receive Activity Starts t25 Time to Deassert COL; LU3X54FT Is Transmitting; Receive Activity Ceases t26 Time to Assert COL; LU3X54FT Is Receiving; Transmit Activity Starts t27 Time to Deassert COL; LU3X54FT Is Receiving; Transmit Activity Ceases t28 COL Pulse Width (TRANSMITTING—RECEIVE COLLISION DETECTED) TX_EN TPIN ...

Page 48

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Timing Characteristics (Preliminary) Table 34. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load) Name t29 RXD Setup Before RX_CLK Rising Edge t30 RXD Held Past RX_CLK Edge t31 RX_CLK Low to CRS Deassertion (at end of received packet) ...

Page 49

... RX_CLK High Pulse Width t38 TX_CLK Low Pulse Width t39 TX_CLK High Pulse Width RX_CLK TX_CLK Figure 18. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX (continued) Parameter t36 t37 t38 t39 LU3X54FT Min Max Unit 5-2737(F) ...

Page 50

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Timing Characteristics (Preliminary) Table 36. 100 Mbits/s MII Transmit Timing Name t40 Rising Edge of TX_CLK Following TX_EN Assertion to CRS Assertion t41 Rising Edge of TX_CLK Following TX_EN Assertion to TPOUT t42 Rising Edge of TX_CLK Following TX_EN Deassertion to CRS Deassertion TX_CLK ...

Page 51

... BIT OF J TPIN t43 CRS RX_CLK t44 RX_DV RX_ER RXD[3:0] Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX (continued) Parameter 1st BIT OF T Figure 20. 100 Mbits/s MII Receive Timing LU3X54FT Min Max — 170 — 210 — 210 — 210 t45 t46 Unit ns ...

Page 52

... LU3X54FT QUAD-FET for 10Base-T/100Base-TX/FX Outline Diagram 208-Pin SQFP Dimensions are in millimeters. 30.60 ± 0.20 28.00 ± 0.20 PIN #1 IDENTIFIER ZONE 208 DETAIL A 0.50 TYP 52 157 156 28.00 ± 0.20 ± 0.20 105 104 DETAIL B 3.40 ± 0.20 4.10 MAX 0.25 MIN ...

Page 53

... Data Sheet July 2000 Ordering Information Device Code Comcode LU3X54FT-HS208 108193384 LU3X54FT-S208 108297334 *Refer to package and thermal characteristics Lucent Technologies Inc. QUAD-FET for 10Base-T/100Base-TX/FX Package 208-Pin SQFPH (Heat Spreader) 208-Pin SQFP LU3X54FT Temperature ...

Page 54

For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA ...

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