HD64F3434TF16 Renesas Electronics Corporation., HD64F3434TF16 Datasheet
HD64F3434TF16
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HD64F3434TF16 Summary of contents
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To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April ...
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Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may ...
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Hitachi Single-Chip Microcomputer ADE-602-077F Rev. 7.0 3/14/03 Hitachi, Ltd. H8/3437 Series H8/3437 HD6473437, HD6433437 H8/3436 HD6433436 H8/3434 HD6473434, HD6433434 H8/3437W HD6433437W H8/3436W HD6433436W H8/3434W HD6433434W H8/3437F-ZTAT™ HD64F3437 H8/3437SF-ZTAT™ HD64F3437S H8/3434F-ZTAT™ HD64F3434 Hardware Manual The revision list can be viewed directly ...
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Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used ...
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The H8/3437 Series is a high-performance single-chip microcomputer that integrates peripheral functions necessary for system configuration with an H8/300 CPU featuring a 32-bit internal architecture as its core. On-chip peripheral functions include ROM, RAM, four kinds of timers, a serial ...
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User's Manuals on the H8/3437 Series: Manual Title H8/3437 Series Hardware Manual H8/300 Series Programming Manual Users manuals for development tools: Manual Title C/C++ Compiler, Assembler, Optimized Linkage Editor User's Manual Simulator Debugger Users Manual Hitachi Debugging Interface Users Manual ...
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Specification) There are two versions of the H8/3437F with on-chip flash memory: a dual-power-supply version and a single-power-supply (S-mask) version. Points to be noted when using the H8/3437F single- power-supply S-mask model are given below. 1. Notes on Voltage ...
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Product Type Names and Markings Table 1 shows examples of product type names and markings for the H8/3437F (dual-power- supply specification) and H8/3437SF (single-power-supply specification), and the differences in flash memory programming power supply. Table 1 Differences in H8/3437F ...
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Differences in S-Mask Model Table 2 shows the differences between the H8/3437F (dual-power-supply specification) and H8/3437SF (single-power-supply specification). Table 2 Differences between H8/3437F and H8/3437F S-Mask Model Dual-Power-Supply Model: Item H8/3437F Program must be applied from off-chip ...
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Dual-Power-Supply Model: Item H8/3437F Programming mode timing RES Prewrite Required before erasing processing Programming Block corresponding to programming processing address must be set in EBR1/EBR2 registers before programming EBR register EBR1, EBR2 configuration Memory ...
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Dual-Power-Supply Model: Item H8/3437F MDCR — — — WSCR RAMS RAM0 CKDBL FLMCR1 7 6 — — FLMCR2 — EBR1 7 6 LB7 LB6 LB5 EBR2 SB7 SB6 SB5 ...
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Table 3 shows differences in the development environments of the H8/3437F (dual-power-supply specification) and H8/3437SF (single-power-supply specification). Table 3 H8/3437F and H8/3437F S-Mask Model Development Environments Dual-Power-Supply Model: Item H8/3437F E6000 Emulator Hitachi emulator unit HS3008EPI60H User Hitachi cable HS3437ECH61H ...
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List of Items Revised or Added for This Version Section Page Notes on S-Mask Model (Single-Power-Supply Specification) 1.1 Overview 3 4 1.3.1 Pin Arrangement 6 6.2.2 Oscillator Circuit (H8/3437SF) 12.3.2 Asynchronous 264 Mode 2 Section 13 I ...
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Section Page 21.1.7 Flash Memory 504 Operating Modes 505 506 21.2.3 Erase Block 511 Register 2 (EBR2) 21.3.1 Boot Mode 516 517 21.4 to 21.4.4 520 to 524 21.5.1 Writer Mode 528 Setting 21.5.3 Operation in 538 Writer Mode 21.6 ...
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Section 1 Overview ........................................................................................................... 1.1 Overview............................................................................................................................ 1.2 Block Diagram................................................................................................................... 1.3 Pin Assignments and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ Section 2 CPU ..................................................................................................................... 19 2.1 Overview............................................................................................................................ 19 2.1.1 Features ................................................................................................................ 19 2.1.2 Address Space ...................................................................................................... 20 2.1.3 ...
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Section 3 MCU Operating Modes and Address Space 3.1 Overview............................................................................................................................ 57 3.1.1 Mode Selection..................................................................................................... 57 3.1.2 Mode and System Control Registers .................................................................... 57 3.2 System Control Register (SYSCR).................................................................................... 58 3.3 Mode Control Register (MDCR) ....................................................................................... 60 3.4 Address Space Map ...
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Section 7 I/O Ports ............................................................................................................ 101 7.1 Overview............................................................................................................................ 101 7.2 Port 1.................................................................................................................................. 104 7.2.1 Overview .............................................................................................................. 104 7.2.2 Register Configuration and Descriptions ............................................................. 105 7.2.3 Pin Functions in Each Mode ................................................................................ 107 7.2.4 Input Pull-Up Transistors ..................................................................................... 109 7.3 Port ...
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Register Configuration and Descriptions ............................................................. 146 7.11.3 Pin Functions in Each Mode ................................................................................ 148 7.11.4 Input Pull-Up Transistors ..................................................................................... 149 7.12 Port B ................................................................................................................................. 150 7.12.1 Overview .............................................................................................................. 150 7.12.2 Register Configuration and Descriptions ............................................................. 151 7.12.3 Pin Functions ...
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Register Descriptions......................................................................................................... 192 9.2.1 Timer Counter (TCNT) ........................................................................................ 192 9.2.2 Time Constant Registers A and B (TCORA and TCORB).................................. 192 9.2.3 Timer Control Register (TCR) ............................................................................. 193 9.2.4 Timer Control/Status Register (TCSR) ................................................................ 196 9.2.5 Serial/Timer Control Register (STCR) ...
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Timer Control/Status Register (TCSR) ................................................................ 224 11.2.3 System Control Register (SYSCR) ...................................................................... 226 11.2.4 Register Access .................................................................................................... 226 11.3 Operation ........................................................................................................................... 227 11.3.1 Watchdog Timer Mode ........................................................................................ 227 11.3.2 Interval Timer Mode ............................................................................................ 228 11.3.3 Setting the Overflow Flag ...
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Input/Output Pins.................................................................................................. 286 13.1.4 Register Configuration ......................................................................................... 286 13.2 Register Descriptions......................................................................................................... 287 2 13.2 Bus Data Register (ICDR).............................................................................. 287 13.2.2 Slave Address Register (SAR) ............................................................................. 287 2 13.2 Bus Mode Register (ICMR) ........................................................................... 288 2 ...
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Section 15 A/D Converter 15.1 Overview............................................................................................................................ 335 15.1.1 Features ................................................................................................................ 335 15.1.2 Block Diagram...................................................................................................... 336 15.1.3 Input Pins.............................................................................................................. 337 15.1.4 Register Configuration ......................................................................................... 338 15.2 Register Descriptions......................................................................................................... 339 15.2.1 A/D Data Registers (ADDRA to ADDRD).............................................. 339 15.2.2 ...
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Socket Adapter Pin Assignments and Memory Map ........................................... 365 18.3 PROM Programming ......................................................................................................... 368 18.3.1 Programming and Verification ............................................................................. 368 18.3.2 Notes on Programming......................................................................................... 373 18.3.3 Reliability of Programmed Data .......................................................................... 374 Section 19 ROM (32-kbyte Dual-Power-Supply Flash Memory ...
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Features ................................................................................................................ 438 20.1.4 Block Diagram...................................................................................................... 439 20.1.5 Input/Output Pins.................................................................................................. 440 20.1.6 Register Configuration ......................................................................................... 440 20.2 Flash Memory Register Descriptions ................................................................................ 441 20.2.1 Flash Memory Control Register (FLMCR).......................................................... 441 20.2.2 Erase Block Register 1 (EBR1)............................................................................ 442 20.2.3 Erase ...
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On-Board Programming Modes ........................................................................................ 513 21.3.1 Boot Mode............................................................................................................ 513 21.3.2 User Programming Mode ..................................................................................... 519 21.4 Programming/Erasing Flash Memory................................................................................ 520 21.4.1 Program Mode...................................................................................................... 520 21.4.2 Program-Verify Mode .......................................................................................... 521 21.4.3 Erase Mode........................................................................................................... 523 21.4.4 Erase-Verify Mode ............................................................................................... 523 21.4.5 ...
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DC Characteristics................................................................................................ 580 23.4.2 AC Characteristics................................................................................................ 585 23.4.3 A/D Converter Characteristics ............................................................................. 591 23.4.4 D/A Converter Characteristics ............................................................................. 592 23.4.5 Flash Memory Characteristics.............................................................................. 593 23.5 MCU Operational Timing.................................................................................................. 595 23.5.1 Bus Timing ........................................................................................................... 595 23.5.2 Control Signal Timing.......................................................................................... 596 ...
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Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix F Option Lists Appendix G Product Code Lineup Appendix H Package Dimensions ............................................................... 715 .................................................................................................. 716 ................................................................................. 718 .................................................................................. 720 xiii ...
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Overview The H8/3437 Series of single-chip microcomputers features an H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit- manipulation ...
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Table 1.1 Features Item Specification CPU Two-way general register configuration Eight 16-bit registers, or Sixteen 8-bit registers High-speed operation Maximum clock rate (ø clock): 16 MHz MHz MHz ...
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Item Specification Serial communication Asynchronous or synchronous mode (selectable) interface (SCI) Full duplex: can transmit and receive simultaneously (2 channels) On-chip baud rate generator bus interface Conforms to Philips I (1 channel) [option] Includes single master mode ...
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... HD6433437F16 HD6433437VF10 HD6433437F12 HD6433437TF16 HD6433437VTF10 HD6433437TF12 HD6433436F16 HD6433436VF10 HD6433436F12 HD6433436TF16 HD6433436VTF10 HD6433436TF12 HD64F3434F16 HD64F3434F16 HD64F3434FLH16 HD64F3434FLH16 HD64F3434TF16 HD64F3434TF16 HD64F3434TFLH16 HD64F3434TFLH16 HD6473434F16 HD6473434F16 HD6473434TF16 HD6473434TF16 HD6433434F16 HD6433434VF10 HD6433434F12 HD6433434TF16 HD6433434VTF10 HD6433434TF12 2 C bus interface include the part number. HD6433437WTF, HD6433434WF, etc. Package ...
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Block Diagram Figure 1.1 shows a block diagram of the H8/3437 Series. PA /KEYIN /KEYIN /KEYIN /KEYIN /KEYIN /KEYIN /KEYIN 6 ...
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Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement of the FP-100B and TFP-100B packages ...
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Pin Functions Pin Assignments in Each Operating Mode: Table 1.2 lists the assignments of the pins of the FP-100B and TFP-100B packages in each operating mode. Table 1.2 Pin Assignments in Each Operating Mode Pin No. Expanded Modes FP-100B, ...
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Pin No. Expanded Modes FP-100B, TFP-100B Mode /IRQ when HIF is disabled or STAC bit STCR EIOW/IRQ when HIF is enabled and STAC bit STCR /IRQ ...
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Pin No. Expanded Modes FP-100B, TFP-100B Mode /AN / /KEYIN /KEYIN /TMCI /TMO ...
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Pin No. Expanded Modes FP-100B, TFP-100B Mode /XDB ...
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Pin No. Expanded Modes FP-100B, TFP-100B Mode /IRQ /TxD when HIF is disabled or STAC bit STCR IOW/IRQ when HIF is enabled and STAC bit STCR 3 98 ...
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Pin Functions: Table 1.3 gives a concise description of the function of each pin. Table 1.3 Pin Functions Type Symbol Power Clock XTAL EXTAL ø RES System control RESO STBY Address bus A ...
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Type Symbol WAIT Bus control NMI Interrupt signals IRQ to 0 IRQ 7 Operating mode MD 1 control MD 0 Pin No. FP-100B, TFP-100B I/O Name and Function 16 I Wait: Requests the CPU to insert wait ...
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Type Symbol 16-bit free- FTOA running timer FTOB (FRT) FTCI FTIA to FTID 8-bit timer TMO 0 TMO 1 TMCI 0 TMCI 1 TMRI 0 TMRI 1 PWM timer Serial communi- TxD 0 cation interface TxD ...
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Type Symbol Host interface HA 0 (HIF HIRQ 1 HIRQ 11 HIRQ 12 Keyboard control KEYIN to 0 KEYIN 15 Host interface XDB to 0 (expanded XDB 7 modes) ECS Host interface 2 (if enabled when STAC bit ...
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Type Symbol Flash memory FV PP [H8/3434, H8/3437 F-ZTAT bus interface SCL [option] SDA I/O ports ...
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Type Symbol I/O ports Note: In this chip, except for the S-mask model (single-power-supply specification), the same pin is used for STBY and FV standby mode. This ...
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18 ...
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Overview The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed operation. 2.1.1 Features The main features of the H8/300 CPU ...
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Address Space The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code and data combined. The memory map differs depending on the mode (mode 3). For details, see section ...
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Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as data ...
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Bit 5—Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B, SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared to 0 otherwise. Similarly set to ...
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Data Formats The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. Bit manipulation instructions operate on 1-bit data specified as bit ..., ...
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Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No 1-bit data RnH 1-bit data RnL 7 Byte data RnH MSB ...
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Memory Data Formats Figure 2.4 indicates the data formats in memory. Word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded ...
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Addressing Modes 2.4.1 Addressing Mode The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No. Addressing Mode (1) Register direct (2) Register indirect (3) Register indirect with displacement ...
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Register Indirect with Pre-Decrement—@–Rn The @–Rn mode is used with MOV instructions that store register contents to memory similar to the register indirect mode, but the 16-bit general register specified in the register field of the instruction is ...
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Calculation of Effective Address Table 2.2 shows how the H8/300 calculates effective addresses in each addressing mode. Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B, ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also ...
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Table 2.2 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct regm regn 2 Register indirect, @ reg 3 Register indirect with displacement, @(d:16, ...
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Addressing Mode and No. Instruction Format 5 Absolute address @aa abs @aa: abs 6 Immediate #xx IMM #xx: IMM 7 PC-relative @(d:8, PC disp ...
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Addressing Mode and No. Instruction Format 8 Memory indirect, @@aa abs Legend: reg: General register op: Operation code disp: Displacement IMM: Immediate data abs: Absolute address Effective Address Calculation H'00 Memory contents ...
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Instruction Set The H8/300 CPU has 57 types of instructions, which are classified by function in table 2.3. Table 2.3 Instruction Classification Function Instructions Data transfer MOV, MOVTPE Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, ...
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The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. Operation Notation Rd General register (destination) Rs General register (source) Rn General ...
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Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* MOV B/W MOVTPE B MOVFPE B PUSH W POP W Note: * Size: Operand size ...
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Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.5 ...
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Arithmetic Operations Table 2.5 describes the arithmetic instructions. See figure 2.6 in section 2.5.4, Shift Operations, for their object codes. Table 2.5 Arithmetic Instructions Instruction Size* ADD B/W SUB ADDX B SUBX INC B DEC ADDS W SUBS DAA ...
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Logic Operations Table 2.6 describes the four instructions that perform logic operations. See figure 2.6 in section 2.5.4, Shift Operations, for their object codes. Table 2.6 Logic Operation Instructions Instruction Size* AND XOR B NOT B ...
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Legend: op: Operation field rm, rn: Register field IMM: Immediate data Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes ...
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Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* BSET B BCLR B BNOT B BTST B BAND B BIAND BOR B BIOR BXOR B Note: * ...
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Instruction Size* BIXOR B BLD B BILD BST B BIST Note: * Size: Operand size B: Byte Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read- modify-write instructions. They read a byte of data, modify one ...
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Before Execution of BCLR Instruction Input/output Input Input Pin state Low High DDR Execution of BCLR Instruction BCLR #0, @P4DDR After Execution of BCLR Instruction Input/output Output Output Pin ...
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Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 ...
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Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont IMM ...
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Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Bcc — JMP — JSR — BSR — RTS — 44 Function Branches if condition cc is true. ...
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Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes 8 7 disp 8 ...
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System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* RTE — SLEEP — LDC B STC B ANDC B ORC B XORC B NOP ...
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Block Data Transfer Instruction Table 2.11 describes the EEPMOV instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction/EEPROM Write Operation Instruction Size EEPMOV — 15 Legend: op: Operation field Figure 2.10 Block Data Transfer ...
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Notes on EEPMOV Instruction 1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified the address specified by R6 R4L 2. ...
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CPU States 2.6.1 Overview The CPU has three states: the program execution state, exception-handling state, and power-down state. The power-down state is further divided into three modes: sleep mode, software standby mode, and hardware standby mode. Figure 2.11 summarizes ...
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Exception handling request Exception- handling state RES = 1 Reset state A transition to the reset state occurs when RES goes low, except when the chip Notes the hardware standby mode. A transition from any state to ...
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Power-Down State The power-down state includes three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU register contents remain unchanged and the on-chip ...
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Internal address bus Internal read signal Internal data bus (read) Internal write signal Internal data bus (write) Figure 2.13 On-Chip Memory Access Cycle ø Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 2.14 ...
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Access to On-Chip Register Field and External Devices The on-chip supporting module registers and external devices are accessed in a cycle consisting of three states and T . Only one byte of data can be ...
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Address bus AS: High RD: High WR: High Data bus: high impedance state Figure 2.16 Pin States during On-Chip Register Field Access Cycle ø Address bus AS RD WR: High Data bus Figure 2.17 (a) External Device Access Timing ...
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T 1 ø Address bus AS RD: High WR Data bus Figure 2.17 (b) External Device Access Timing (Write) Write cycle state T state 2 Address Write data T state 3 55 ...
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Section 3 MCU Operating Modes and Address Space 3.1 Overview 3.1.1 Mode Selection The H8/3437 Series operates in three modes numbered 1, 2, and 3. The mode is selected by the inputs at the mode pins (MD 1 Table 3.1 ...
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System Control Register (SYSCR) Bit 7 SSBY STS2 Initial value 0 Read/Write R/W The system control register (SYSCR 8-bit register that controls the operation of the chip. Bit 7—Software Standby (SSBY): Enables transition to the software standby ...
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F-ZTAT Version Bit 6: STS2 Bit 5: STS1 Note: When 1,024 states (STS2 to STS0 = 101) is selected, the following points should be noted period exceeding øp/1,024 (e.g. øp/2,048) is specified ...
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Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by a reset, but is not initialized in the software standby mode. Bit 0: RAME Description 0 The on-chip RAM is disabled. 1 The on-chip ...
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Address Space Map in Each Operating Mode Figures 3.1 and 3.2 show memory maps of the H8/3437, H8/3436, and H8/3434 in modes 1, 2, and 3. Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'004B H'004C External ...
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'004B H'004C External address space H'F77F H'F780 On-chip RAM *2 , 2,048 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF Notes not access reserved ...
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Mode 1 Expanded Mode without On-Chip ROM H'0000 Vector table H'004B H'004C External address space H'F77F H'F780 *1, *2 Reserved H'FB7F H'FB80 *2 On-chip RAM , 1,024 bytes H'FF7F H'FF80 External address space H'FF87 H'FF88 On-chip register field H'FFFF Notes: ...
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Section 4 Exception Handling 4.1 Overview The H8/3437 Series recognizes two kinds of exceptions: interrupts and the reset. Table 4.1 indicates their priority and the timing of their hardware exception-handling sequence. Table 4.1 Hardware Exception-Handling Sequences and Priority Type of ...
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The following sequence is carried out when reset exception handling begins. 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit in the condition code register (CCR) is set ...
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Figure 4.2 Reset Sequence (Mode 1) 67 ...
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Disabling of Interrupts after Reset After a reset interrupt were to be accepted before initialization of the stack pointer (SP: R7), the program counter and condition code register might not be saved correctly, leading to a program ...
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Table 4.2 Interrupts Interrupt source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16-bit free-running ICIA (Input capture A) timer ICIB (Input capture B) ICIC (Input capture C) ICID (Input capture D) OCIA (Output compare A) OCIB (Output compare ...
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Interrupt-Related Registers The interrupt-related registers are the system control register (SYSCR), IRQ sense control register (ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask registers (KMIMR and KMIMRA). Table 4.3 Registers Read by Interrupt Controller Name System control ...
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Bits 7 to 0—IRQ to IRQ Sense Control (IRQ7SC to IRQ0SC): These bits determine whether 7 0 IRQ to IRQ are level-sensed or sensed on the falling edge Bits IRQ7SC to IRQ0SC Description An interrupt ...
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Keyboard Matrix Interrupt Mask Register (KMIMR) To control interrupts from a 16 there are two keyboard matrix interrupt mask registers, KMIMR and KMIMRA. Bits KMIMR7 to KMIMR0 in KMIMR correspond to key-sense inputs KEYIN KMIMR8 in KMIMRA correspond to key-sense ...
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Figure 4.3 shows the relationship between the IRQ KMIMR0 (1) P6 /KEYIN KMIMR6 (0) P6 /KEYIN /IRQ KMIMR7 (1) P6 /KEYIN 7 7 KMIMR8 (1) PA /KEYIN ...
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External Interrupts The nine external interrupts are NMI and IRQ used to recover from software standby mode. NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal regardless of whether the I ...
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Interrupt Handling Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt requests, commands the CPU to start the hardware interrupt exception-handling sequence, and furnishes the necessary vector number. Figure 4.4 shows a block diagram of the ...
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When an NMI or another enabled interrupt is requested, the interrupt controller transfers the interrupt request to the CPU and indicates the corresponding vector number. (When two or more interrupts are requested, the interrupt controller selects the vector number of ...
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Program execution Interrupt requested? Yes NMI IRQ ? 0 Yes IRQ Yes Latch vector no. Save PC Save CCR Reset I 1 Read vector address Branch to software interrupt-handling routine Figure 4.5 Hardware Interrupt-Handling Sequence No ...
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SP – – – – (R7) Stack area Before interrupt is accepted PC: Program counter CCR: Condition code register SP: Stack pointer Notes: 1. The PC contains the address of the first ...
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Interrupt accepted Interrupt priority decision. Wait for Instruction end of instruction. prefetch Interrupt request signal ø Internal address (1) bus Internal read signal Internal write signal Internal 16-bit (2) data bus (1) Instruction prefetch address (Pushed on stack. Instruction is ...
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Interrupt Response Time Table 4.4 indicates the number of states that elapse from an interrupt request signal until the first instruction of the software interrupt-handling routine is executed. Since on-chip memory is accessed 16 bits at a time, very ...
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Precaution Note that the following type of contention can occur in interrupt handling. When software clears the enable bit of an interrupt disable the interrupt, the interrupt becomes disabled after execution of the clearing instruction. If ...
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Note on Stack Handling In word access, the least significant bit of the address is always assumed The stack is always accessed by word access. Care should be taken to keep an even value in the ...
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Section 5 Wait-State Controller 5.1 Overview The H8/3437 Series has an on-chip wait-state controller that enables insertion of wait states into bus cycles for interfacing to low-speed external devices. 5.1.1 Features Features of the wait-state controller are listed below. Three ...
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Input/Output Pins Table 5.1 summarizes the wait-state controller’s input pin. Table 5.1 Wait-State Controller Pins Name Abbreviation WAIT Wait 5.1.4 Register Configuration Table 5.2 summarizes the wait-state controller’s register. Table 5.2 Register Configuration Address Name H'FFC2 Wait-state control register ...
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Bit 7—RAM Select (RAMS) Bit 6—RAM Area Select (RAM0) Bits 7 and 6 select a RAM area for emulation of dual-power-supply flash memory updates. For details, see the flash memory description in section 19, 20, ROM. Bit 5—Clock Double (CKDBL): ...
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Wait Modes Programmable Wait Mode: The number of wait states (T inserted in all accesses to external addresses. Figure 5.2 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). ø Address bus AS ...
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Pin Wait Mode: In all accesses to external addresses, the number of wait states (T bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock (ø) in the last of these ...
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Pin Auto-Wait Mode: If the WAIT pin is low, the number of wait states (T WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock (ø) in the ...
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Section 6 Clock Pulse Generator 6.1 Overview The H8/3437 Series has a built-in clock pulse generator (CPG) consisting of an oscillator circuit, a duty adjustment circuit, and a divider and a prescaler that generates clock signals for the on-chip supporting ...
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Wait-State Control Register (WSCR) WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals supplied to the supporting modules. It also controls wait state controller wait settings, RAM area setting for dual-power-supply flash memory, and ...
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Oscillator Circuit 6.2.1 Oscillator (Generic Device external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator circuit generates a system clock signal. Alternatively, an external clock signal can be applied to the EXTAL pin. ...
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XTAL Figure 6.3 Equivalent Circuit of External Crystal Table 6.2 External Crystal Parameters Frequency (MHz max ( ) 500 C (pF max 0 Use a crystal with the same frequency as the desired system clock frequency ...
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Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6.5. In example (b) in figure 6.5, the external clock signal should be kept high during standby. If the ...
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External Clock Input: The external clock signal should have the same frequency as the desired system clock (ø). Clock timing parameters are given in table 6.3 and figure 6.6. Table 6.3 Clock Timing V 5.5 V Item Symbol Min Low ...
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Table 6.4 External Clock Output Stabilization Delay Time Conditions 2 Item External clock output stabilization delay time Note includes DEXT cyc V 2 STBY IH ...
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EXTAL XTAL Figure 6.8 Connection of Crystal Oscillator (Example) Table 6.5 Damping Resistance Frequency (MHz) Rd max ( ) Crystal Oscillator: Figure 6.9 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in ...
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Not allowed Figure 6.10 Notes on Board Design around External Crystal Input of External Clock Signal Circuit Configuration: An external clock signal can be input as shown in the examples in figure 6.11. In example (b) ...
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External Clock Input: The external clock signal should have the same frequency as the desired system clock (ø). Clock timing parameters are given in table 6.7 and figure 6.12. Table 6.7 Clock Timing Item Low pulse width of external clock ...
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Table 6.8 External Clock Output Stabilization Delay Time Conditions 3 Item External clock output stabilization delay time Note includes DEXT cyc V 3 STBY IH ...
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100 ...
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Overview The H8/3437 Series has eight 8-bit input/output ports, one 7-bit input/output port, and one 3-bit input/output port, and are 8-bit input port. Table 7.1 lists the functions of each port in each operating mode. As table 7.1 indicates, ...
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Table 7.1 Port Functions Port Description Pins Port 1 8-bit I/O port P1 Can drive LEDs Built-in input pull-ups Port 2 8-bit I/O port P2 Can drive LEDs Built-in input pull-ups Port 3 8-bit I/O port P3 D Built-in input ...
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Port Description Pins Port 8 7-bit I/O port P8 Can drive a bus P8 line ( Port 9 8-bit I/O port P9 Can drive a bus line ( ...
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Port 1 7.2.1 Overview Port 8-bit input/output port with the pin configuration shown in figure 7.1. The pin functions differ depending on the operating mode. Port 1 has built-in, programmable MOS input pull-up transistors that can ...
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Register Configuration and Descriptions Table 7.2 summarizes the port 1 registers. Table 7.2 Port 1 Registers Name Port 1 data direction register Port 1 data register Port 1 input pull-up control register Port 1 Data Direction Register (P1DDR) Bit ...
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Port 1 Data Register (P1DR) Bit Initial value 0 Read/Write R/W P1DR is an 8-bit register that stores data for pins read, the value in P1DR is obtained directly, regardless of the actual pin ...
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Pin Functions in Each Mode Port 1 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 ...
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Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower address output pins and general input pins. Each pin becomes a lower address output pin if its P1DDR bit is set to 1, and ...
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Input Pull-Up Transistors Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode ...
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Port 2 7.3.1 Overview Port 8-bit input/output port with the pin configuration shown in figure 7.5. The pin functions differ depending on the operating mode. Port 2 has built-in, programmable MOS input pull-up transistors that can ...
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Register Configuration and Descriptions Table 7.4 summarizes the port 2 registers. Table 7.4 Port 2 Registers Name Port 2 data direction register Port 2 data register Port 2 input pull-up control register Port 2 Data Direction Register (P2DDR) Bit ...
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Port 2 Data Register (P2DR) Bit Initial value 0 Read/Write R/W P2DR is an 8-bit register that stores data for pins read, the value in P2DR is obtained directly, regardless of the actual pin ...
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Pin Functions in Each Mode Port 2 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 ...
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Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper address output pins and general input pins. Each pin becomes an upper address output pin if its P2DDR bit is set to 1, and ...
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Input Pull-Up Transistors Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode ...
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Port 3 7.4.1 Overview Port 8-bit input/output port that is multiplexed with the data bus and host interface data bus. Figure 7.9 shows the pin configuration of port 3. The pin functions differ depending on the ...
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Register Configuration and Descriptions Table 7.6 summarizes the port 3 registers. Table 7.6 Port 3 Registers Name Port 3 data direction register Port 3 data register Port 3 input pull-up control register Port 3 Data Direction Register (P3DDR) Bit ...
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Port 3 Data Register (P3DR) Bit Initial value 0 Read/Write R/W P3DR is an 8-bit register that stores data for pins read, the value in P3DR is obtained directly, regardless of the actual pin ...
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Pin Functions in Each Mode Port 3 has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) ...
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Mode 3: In mode 3 (single-chip mode), when the host interface enable bit (HIE) is cleared the system control register (SYSCR), port general-purpose input/output port. A pin becomes an output pin when its P3DDR ...
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Port 4 7.5.1 Overview Port 8-bit input/output port that is multiplexed with input/output pins (TMRI TMCI , TMCI , TMO , TMO and 1. In slave mode host ...
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Register Configuration and Descriptions Table 7.8 summarizes the port 4 registers. Table 7.8 Port 4 Registers Name Port 4 data direction register Port 4 data register Port 4 Data Direction Register (P4DDR) Bit 7 P4 DDR P4 7 Initial ...
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Port 4 Data Register (P4DR) Bit Initial value 0 Read/Write R/W P4DR is an 8-bit register that stores data for pins read, the value in P4DR is obtained directly, regardless of the actual pin ...
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Pin Functions Port 4 has different pin functions depending on whether the chip not operating in slave mode. Table 7.9 indicates the pin functions of port 4. Table 7.9 Port 4 Pin Functions Pin Pin Functions ...
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Pin Pin Functions and Selection Method P4 /TMCI / Bit P4 DDR and the operating mode select the pin function as follows HIRQ P4 DDR 11 3 Operating mode Pin function Note: * TMCI select an external ...
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Port 5 7.6.1 Overview Port 3-bit input/output port that is multiplexed with input/output pins (TxD serial communication interface 0. The port 5 pin functions are the same in all operating modes. Figure 7.13 shows the pin ...
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Port 5 Data Direction Register (P5DDR) Bit 7 — Initial value 1 Read/Write — P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin functions as an output pin if the corresponding ...
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Pin Functions Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI0 input/output pins. Table 7.11 indicates the pin functions of port 5. Table 7.11 Port 5 Pin Functions Pin ...
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Port 6 7.7.1 Overview Port 8-bit input/output port that is multiplexed with input/output pins (FTOA, FTOB, FTIA to FTID, FTCI) of the 16-bit free-running timer (FRT), with key-sense input pins, and with IRQ and IRQ input ...
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Port 6 Data Direction Register (P6DDR) Bit 7 P6 DDR P6 7 Initial value 0 Read/Write W P6DDR is an 8-bit register that controls the input/output direction of each pin in port 6. A pin functions as an output pin ...
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Port 6 Input Pull-Up Control Register (KMPCR) Bit 7 KM PCR KM 7 Initial value 0 Read/Write R/W KMPCR is an 8-bit readable/writable register that controls the input pull-up transistors in port P6DDR bit is cleared to ...
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Pin Functions Port 6 has the same pin functions in all operating modes. The pins are multiplexed with FRT input/output, IRQ and IRQ input, and key-sense input. Table 7.13 indicates the pin functions port 6. Table ...
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Pin Pin Functions and Selection Method P6 /FTIB/ 3 KEYIN P6 DDR 3 3 Pin function P6 /FTIA/ 2 KEYIN P6 DDR 2 2 Pin function P6 /FTOA/ Bit OEA in TOCR of the FRT and bit P6 1 KEYIN ...
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Input Pull-Up Transistors Port 6 has built-in programmable input pull-up transistors. The pull-up for each bit can be turned on and off individually. To turn on an input pull-up, set the corresponding KMPCR bit to 1 and clear the ...
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Port 7 7.8.1 Overview Port 8-bit input port that also provides the analog input pins for the A/D converter and analog output pins for the D/A converter. The pin functions are the same in all modes. ...
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Port 7 Input Data Register (P7PIN) Bit Initial value —* Read/Write R Note: * Depends on the levels of pins P7 When P7PIN is read, the pin states are always read. P7PIN is a read-only register and ...
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Port 8 pins P8 /SCK /IRQ /RxD /IRQ /TxD /IRQ 4 1 Port 8 P8 /IOR Pin configuration in slave mode ...
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Port 8 Data Direction Register (P8DDR) Bit 7 — P8 Initial value 1 Read/Write — P8DDR is an 8-bit register that controls the input/output direction of each pin in port 8. A pin functions as an output pin if the ...
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Pin Functions Pins are multiplexed with HIF input/output, SCI1 input/output and IRQ to IRQ input. Table 7.17 indicates the functions of pins Table 7.17 Port 8 Pin Functions Pin Pin ...
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Pin Pin Functions and Selection Method P8 /IRQ / Bit TE in SCR of SCI1, bit STAC in STCR, bit IOW/TxD select the pin function as follows 1 Operating mode STAC TE P8 DDR 4 Pin function ...
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Port 9 7.10.1 Overview Port 8-bit input/output port that is multiplexed with interrupt input pins (IRQ input/output pins for bus control signals (RD, WR, AS, WAIT), an input pin (ADTRG) for the A/D converter, an output ...
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Port 9 P9 /IRQ 1 P9 /IRQ 0 Figure 7.17 Port 9 Pin Configuration (cont) 7.10.2 Register Configuration and Descriptions Table 7.18 summarizes the port 9 registers. Table 7.18 Port 9 Registers Name Port 9 data direction register Port 9 ...
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Port 9 Data Direction Register (P9DDR) Bit 7 P9 DDR P9 7 Modes 1 and 2 Initial value 0 Read/Write W Mode 3 Initial value 0 Read/Write W P9DDR is an 8-bit register that controls the input/output direction of each ...
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Pin Functions Port 9 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode 3. The pins are multiplexed with IRQ input, system clock (ø) output, host interface input ...
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Pin Pin Functions and Selection Method P9 /RD Bit P9 DDR and the operating mode select the pin function as follows 3 3 Operating mode P9 DDR 3 Pin function P9 /IRQ DDR 2 Pin function Note: ...
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Port A 7.11.1 Overview Port 8-bit input/output port that is multiplexed with key-sense input pins. The port A pin functions are the same in all operating modes. Figure 7.18 shows the pin configuration of port A. ...
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Port A Data Direction Register (PADDR) Bit 7 PA DDR PA 7 Initial value 0 Read/Write W PADDR is an 8-bit register that controls the input/output direction of each pin in port A. A pin functions as an output pin ...
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Pin Functions in Each Mode Port A has the same pin functions in all operating modes. Table 7.21 indicates the pin functions of port A. Table 7.21 Port A Pin Functions Pin Pin Functions and Selection Method PA /KEYIN ...
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Pin Pin Functions and Selection Method PA /KEYIN DDR 2 Pin function PA /KEYIN DDR 1 Pin function PA /KEYIN DDR 0 Pin function 7.11.4 Input Pull-Up Transistors Port A has ...
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Port B 7.12.1 Overview Port 8-bit input/output port that is multiplexed with the host interface data bus. The pin functions differ depending on the operating mode. Figure 7.19 shows the pin configuration of port B. Port ...
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Register Configuration and Descriptions Table 7.23 summarizes the port B registers. Table 7.23 Port B Registers Name Port B data direction register Port B output data register Port B input data register Note: The port B data direction register ...
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Port B Output Data Register (PBODR) Bit Initial value 0 Read/Write R/W PBODR is an 8-bit register that stores data for pins PB and read, regardless of the PBDDR settings. PBODR is initialized to H' ...
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Pin Functions in Each Mode Port B has different pin functions in different modes. A separate description for each mode is given below. Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) ...
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Pin Functions in Mode 3: In mode 3 (single-chip mode), each pin can be designated for general input or output. A pin becomes an output pin when its PBDDR bit is set to 1, and an input pin when this ...
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Section 8 16-Bit Free-Running Timer 8.1 Overview The H8/3437 Series has an on-chip 16-bit free-running timer (FRT) module that uses a 16-bit free- running counter as a time base. Applications of the FRT module include rectangular-wave output (up to two ...
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Block Diagram Figure 8.1 shows a block diagram of the free-running timer. Internal clock sources ø External ø clock source ø FTCI Clock select Compare- match A FTOA FTOB Control logic FTIA FTIB FTIC FTID Legend: FRC: Free-running counter ...
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Input and Output Pins Table 8.1 lists the input and output pins of the free-running timer module. Table 8.1 Input and Output Pins of Free-Running Timer Module Name Abbreviation Counter clock input FTCI Output compare A FTOA Output compare ...
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Register Configuration Table 8.2 lists the registers of the free-running timer module. Table 8.2 Register Configuration Name Timer interrupt enable register Timer control/status register Free-running counter (high) Free-running counter (low) Output compare register A/B (high) Output compare register A/B ...
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Register Descriptions 8.2.1 Free-Running Counter (FRC) Bit Initial value Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W FRC is a 16-bit readable/writable up-counter that ...
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Input Capture Registers (ICRA to ICRD) Bit Initial value Read/Write There are four input capture registers each of which is a 16-bit read-only register. ...
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Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB. When input capture is buffered, if the two input edge bits are set to different values (IEDGA IEDGC or IEDGB ...
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Timer Interrupt Enable Register (TIER) Bit 7 ICIAE ICIBE Initial value 0 Read/Write R/W TIER is an 8-bit readable/writable register that enables and disables interrupts. TIER is initialized to H' reset and in the standby modes. Bit ...
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Bit 3—Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1. Bit 3: OCIAE Description 0 Output compare interrupt request A ...
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Timer Control/Status Register (TCSR) Bit 7 ICFA Initial value 0 Read/Write R/(W)* R/(W)* Note: * Software can write bits clear the flags, but cannot write these bits. TCSR is ...
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Bit 5—Input Capture Flag C (ICFC): This status bit is set flag input of a rising or falling edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of the FRC ...
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Bit 2—Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value matches the OCRB value. This flag must be cleared by software set by hardware, however, and cannot be set by software. ...
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Bit 7—Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input capture A signal (FTIA). Bit 7: IEDGA Description 0 Input capture A events are recognized on the falling edge of FTIA. (Initial value) ...
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Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for ICRB. Bit 2: BUFEB Description 0 ICRD is used for input capture D. 1 ICRD is used as a buffer register for input ...
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Bit 3—Output Enable A (OEA): This bit enables or disables output of the output compare A signal (FTOA). Bit 3: OEA Description 0 Output compare A output is disabled. 1 Output compare A output is enabled. Bit 2—Output Enable B ...
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CPU Interface The free-running counter (FRC), output compare registers (OCRA and OCRB), and input capture registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data bus. When the CPU accesses these registers, to ensure ...