CY7C150-10PC Cypress Semiconductor Corporation., CY7C150-10PC Datasheet

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CY7C150-10PC

Manufacturer Part Number
CY7C150-10PC
Description
1Kx4 Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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CY7C150-10PC
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Cypress Semiconductor Corporation
Document #: 38-05024 Rev. *A
Features
Functional Description
The CY7C150 is a high-performance CMOS static RAM de-
signed for use in cache memory, high-speed graphics, and
data-acquisition applications. The CY7C150 has a memory re-
set feature that allows the entire memory to be reset in two
memory cycles.
Selection Guide
• Memory reset function
• 1024 x 4 static RAM for control store in high-speed com-
• CMOS for optimum speed/power
• High speed
• Low power
• Separate inputs and outputs
• 5-volt power supply 10% tolerance in both commercial
• Capable of withstanding greater than 2001V static dis-
• TTL-compatible inputs and outputs
Maximum Access Time (ns)
Maximum Operating Current (mA)
Logic Block Diagram
puters
and military
charge
— 10 ns (commercial)
— 12 ns (military)
— 495 mW (commercial)
— 550 mW (military)
A
A
A
A
A
A
0
1
2
3
4
5
A
COLUMN DECODER
6
DATAINPUT
D
CONTROL
DECODER
COLUMN
0
64 x 64
ARRA Y
A
D
7
1
D
A
2
8
D
3
A
9
Commercial
Military
Commercial
Military
3901 North First Street
C150–1
7C150 10
O
O
RS
CS
OE
WE
O
O
0
1
2
3
10
90
Separate I/O paths eliminates the need to multiplex data in
and data out, providing for simpler board layout and faster sys-
tem performance. Outputs are three-stated during write, reset,
deselect, or when output enable (OE) is held HIGH, allowing
for easy memory expansion.
Reset is initiated by selecting the device (CS = LOW) and tak-
ing the reset (RS) input LOW. Within two memory cycles all
bits are internally cleared to zero. Since chip select must be
LOW for the device to be reset, a global reset signal can be
employed, with only selected devices being cleared at any giv-
en time.
Writing to the device is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
four data inputs (D
specified on the address pins (A
Reading the device is accomplished by taking chip select (CS)
and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory
location specified on the address pins will appear on the four
output pins (O
The output pins remain in high-impedance state when chip
enable (CE) or output enable (OE) is HIGH, or write enable
(WE) or reset (RS) is LOW.
A die coat is used to insure alpha immunity.
7C150 12
San Jose
100
12
12
90
0
GND
O 0
O 1
Pin Configuration
D 0
D 1
A 3
A 4
A 5
A 6
A 7
A 8
A 9
through O
0
D
1
2
3
4
5
6
7
8
9
10
11
12
7C150 15
DIP/SOIC
Top View
3
7C150
) is written into the memory location
100
3
15
15
90
).
1Kx4 Static RAM
CA 95134
24
23
22
21
20
19
18
17
16
15
14
13
0
C150-2
through A
CS
WE
Revised January 18, 2003
V CC
A 2
A 1
A 0
RS
D 3
OE
D 2
O 3
O 2
7C150 25
100
25
25
90
9
CY7C150
).
408-943-2600
7C150 35
100
35
90
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CY7C150-10PC Summary of contents

Page 1

... Capable of withstanding greater than 2001V static dis- charge • TTL-compatible inputs and outputs Functional Description The CY7C150 is a high-performance CMOS static RAM de- signed for use in cache memory, high-speed graphics, and data-acquisition applications. The CY7C150 has a memory re- set feature that allows the entire memory to be reset in two memory cycles ...

Page 2

... OL OUT OH Output Disabled [ Max GND CC OUT V = Max., Commercial OUT Military Test Conditions MHz 5.0V CC R1329 3. 202 GND < JIG AND SCOPE C150–3 (b) 1.9V CY7C150 Ambient Temperature + 10 +125 C 5V 10% 7C150 Min. Max. Unit 2.4 V 0 3 +50 A 300 100 mA Max. ...

Page 3

... HIGH. The data input set-up and hold timing should be reference to the rising edge of the signal that terminates the write. Document #: 38-05024 Rev. *A [2,5] 7C150 10 7C150 12 7C150 15 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max [ less than t for any given device CY7C150 7C150 25 7C150 35 Unit ...

Page 4

... WE is HIGH for read cycle. 10. Device is continuously selected, CS and 11. Address prior to or coincident with CS transition LOW. Document #: 38-05024 Rev OHA DOE DATA VALID SCS PWE t SD DATA VALID IN t HZWE HIGH IMPEDANCE . IL CY7C150 DATA VALID C150-5 t HZOE t HZCS HIGH IMPEDANCE C150 LZWE C150-7 Page [+] Feedback ...

Page 5

... Reset cycle is defined by the overlap of RS and CS for the minimum reset pulse width. Document #: 38-05024 Rev SCS PWE t SD DATA VALID IN t HZWE t RRC t SAR t SWER t t HCSR SCSR t PRS t t HZRS LZRS HIGH IMPEDANCE CY7C150 HIGH IMPEDANCE C150-8 t HAR t HWER OUTPUT VALID ZERO C150-9 Page [+] Feedback ...

Page 6

... AMBIENT TEMPERATURE(°C) TYPICAL ACCESS TIME CHANGE vs.OUTPUT LOADING =4. =25° 200 400 600 800 1000 CAPACITANCE (pF) CY7C150 OUTPUT SOURCE CURRENT vs.OUTPUT VOLTAGE =5. =25° 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE 150 125 ...

Page 7

... CY7C150 12PC P13A CY7C150 12SC S13 CY7C150 12DMB D14 15 CY7C150 15PC P13A CY7C150 15SC S13 CY7C150 15DMB D14 25 CY7C150 25PC P13A CY7C150 25SC S13 CY7C150 25DMB D14 35 CY7C150 35DMB D14 Document #: 38-05024 Rev. *A Mode Not Selected Reset Write Read Output Disable ...

Page 8

... Document #: 38-05024 Rev. *A Switching Characteristics Parameter Subgroups READ CYCLE 10 10 10, 11 OHA 10, 11 ACS WRITE CYCLE 10 10, 11 SCS 10, 11 PWE 10 10 RESET CYCLE 10, 11 RRC 10, 11 SAR 10, 11 SWER 10, 11 SCSR 10, 11 PRS 10, 11 HCSR 10, 11 HWER 10, 11 HAR CY7C150 Page [+] Feedback ...

Page 9

... Package Diagrams Document #: 38-05024 Rev. *A 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 24-Lead (300-Mil) Molded DIP P13/P13A CY7C150 Page [+] Feedback ...

Page 10

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 24-Lead Molded SOIC S13 CY7C150 Page [+] Feedback ...

Page 11

... Document Title: Cy7C150 1K x4 Static RAM Document Number: 38-05024 Issue Orig. of REV. ECN NO. Date Change ** 106810 09/10/01 SZV *A 122462 01/18/03 RBI Document #: 38-05024 Rev. *A Description of Change Change from Spec number: 38-00028 to 38-05024 This ECN/Spec will serve as the master signature approval document for all ECN’ ...

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