CY7B933-LMB Cypress Semiconductor Corporation., CY7B933-LMB Datasheet
CY7B933-LMB
Specifications of CY7B933-LMB
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CY7B933-LMB Summary of contents
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... Single +5V supply • 28-pin SOIC/PLCC/LCC • 0.8 BiCMOS Functional Description The CY7B923 HOTLink™ Transmitter and CY7B933 HOTLink Receiver are point-to-point communications building blocks that transfer data over high-speed serial links (fiber, coax, and CY7B923 Transmitter Logic Block Diagram SC/D (D ...
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... PLCC/LCC Top View 2726 28 BISTEN 5 GND 6 MODE 7 7B923 CCQ SVS 1213 1718 h 7 SERIAL LINK B923–3 Figure 1. HOTLink System Connections CY7B933 Receiver Pin Configurations OUTB+ OUTA+ OUTA BISTEN FOTO ENN ENA V CCQ CKW GND RVS(Q SC/D B923–5 FOTO 25 ENN ...
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... Range 0.5V to +7.0V Commercial Industrial 50 mA Military become ...7 b, c,... control code (Special Character), while a LOW causes the data to be coded input. SVS has the same timing CY7B923 CY7B933 Ambient Temperature + +125 C 5V 10% Case Temperature respectively. ) acts as D input. SC/D has the ...
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... HIGH for all but the last byte of a test loop. RP will pulse LOW one byte time per BIST loop. V Power for output drivers. CCN V Power for internal circuitry. CCQ GND Ground. CY7B933 HOTLink Receiver Name I/O Description Q TTL Out Q Parallel Data Output ...
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... CY7B933 HOTLink Receiver (continued) Name I/O Description INB PECL in Serial Data Input B. This pin is either a single-ended PECL data receiver (INB) or half of the INB (INB+) (Diff In) differential pair wired to V with INA . normally connected and loaded, INB becomes a single-ended PECL 100K (+5V refer- enced) serial data input ...
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... Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic to properly select the data encod- ing. Test logic is discussed in more detail in the CY7B923 HOTLink Transmitter Operating Mode Description CY7B933 HOTLink Receiver Block Diagram Description being the first bit Serial Data Inputs Two pairs of differential line receivers are the inputs for the serial data stream ...
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... Test Logic Test logic includes the initialization and control for the Built-In Self-Test (BIST) generator, the multiplexer for Test mode clock distribution, and control logic for the decoder. Test logic is dis- cussed in more detail in the CY7B933 HOTLink Receiver Op- erating Mode Description 7 CY7B923 ...
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... TTL OUTs, CY7B923: RP; CY7B933 Output HIGH Voltage OHT V Output LOW Voltage OLT I Output Short Circuit Current OST TTL INs, CY7B923 SC/D, SVS, ENA, ENN, CKW, FOTO, BISTEN; CY7B933: RF, REFCLK, BISTEN Input HIGH Voltage IHT V Input LOW Voltage ILT I Input HIGH Current IHT ...
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... B [11] 0 [12 [12 [7] [7] [7, 13] [7, 14] and t minimum timing assures correct data load on rising edge of CKW, but not RP function or timing pF. L 2.0V, over the operating range CY7B923 CY7B933 Max. Unit = 5. = < (Includes fixture and probe capacitance) [8] B923–8 V IHE 80% 80% 20% V ILE < ...
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... [17, 18 0.1 +0.1 6.5 6.5 20 100 0.9t 0.9t B /10 if data is being received. See note. CKW , SC/D, and RVS) are loaded with similar DC and AC loads and V specification (approximately CY7B923 CY7B933 7B933 7B933-400 Max. Min. Max. Unit 3.03 6.25 2.5 6. 2 ...
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... Switching Waveforms for the CY7B923 HOTLink Transmitter CKW ENA D – SC/D, SVS, BISTEN RP t CPWL CKW ENN D – SC/D, SVS, BISTEN t CPWL t SENP t t HENP SD 10,11 NOTES VALID DATA PDF t PDR t PPWH t CKW t CPWH CY7B923 CY7B933 t CKW t CPWH DISABLED ENABLED B923–11 VALID DATA B923– ...
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... Switching Waveforms for the CY7B933 HOTLink Receiver t CPRH CKR t PRH RDY SC/D,RVS, t REFCLK NOTE SO Static Alignment INA , INB SAMPLE WINDOW t CKR t CPRL PRF t CKX CPXL t CPXH 1.5V B923–15 Error-F ree Window INA INB B923–16 12 CY7B923 CY7B933 t ROH B923–13 B923– ...
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... The latency through the transmitter is approximately 21tB 10 ns over the operating range. A more complete description is found in the section CY7B923 HOTLink Transmitter Operating Mode Description . Figure 3 illustrates the data flow through the HOTLink CY7B933 receiver pipeline. Serial data is sampled by the re- SERIAL DATA IN INX DATA CKR ...
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... RVS RDY IS HIGH WHILE WAITING FOR K28.5 RDY Figure 4. CY7B933 Framing Operation in Encoded Mode When the RF pin is asserted HIGH, RDY leaves it normal mode of operation and is asserted HIGH while the framer searches the data stream for a K28.5 character. After the framer has synchronized to a K28 ...
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... An internal voltage comparator detects when an output differential pair is wired to V source for that pair to be disabled. This results in a power savings of around 5 mA for each unused pair. 15 CY7B923 CY7B933 CLOCKED FIFO 7C44X/ ...
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... E Receiver 28 IB IB– IA IA– .01UF Fiber Optic 8 20 PECL Load Figure 6. HOTLink Connection Diagram 16 CY7B923 CY7B933 ) < (peak-peak). Typically mea < 175 ps (peak-peak). Typically measured j .01UF VCC 130 Fiber Optic Fiber Tx TX TX+ TX– 130 GND Coax or Twisted Pair A B 270 270 ...
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... ENN HIGH and resume normal function. Note: It may be advisable to send violation characters to test the RVS output in the Receiver. This can be done by explicitly sending a violation with the SVS input, or allowing the trans- 17 CY7B923 CY7B933 CY7B923 OUTA OUTB OUTC CY7B933 SO DON'T CARE INA INB LOW A/B B923–23 ...
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... HIGH while in Test mode. This forces the two outputs “PECL LOW,” which can be ignored while the test system creates a differential input signal at some higher voltage. CY7B933 HOTLink Receiver Operating Mode Description In normal user operation, the Receiver can operate in either of two modes. The Encoded mode allows a user system to send and receive 8-bit data and control information without first con- verting it to transmission characters ...
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... RDY resumes, the received data will be properly framed and will be decoded correctly. In Bypass mode with RF HIGH, RDY will pulse once for each K28.5 received. For more information on the RDY pin, consult the “HOTLink CY7B933 RDY Pin Description” applica- tion note. Code rule violations and reception errors will be indicated as follows: 1 ...
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... Receiver Test Mode Description The CY7B933 Receiver offers two types of test mode opera- tion, BIST mode and Test mode normal system applica- tion, the Built-In Self-Test (BIST) mode can be used to check the functionality of the Transmitter, the Receiver and the link connecting them. This mode is available with minimal impact on user system logic, and can be used as part of the normal system diagnostics ...
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... It is also positive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is 0011. 2. Running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones also 21 CY7B923 CY7B933 ...
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... Transmission Char- acter in which the error occurred. Table 2 shows an example of this behavior. Character RD Character D21.1 D10.2 101010 1001 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 22 CY7B923 CY7B933 Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 02 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... CY7B923 CY7B933 ...
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... Running Disparity Violation Pattern 111 00100 110111 0101 31 CY7B923 CY7B933 Current RD+ fghj abcdei fghj 110000 1011 110000 0110 110000 1010 110000 1100 110000 1101 110000 0101 110000 1001 110000 ...
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... CY7B923-155JC CY7B923-155JI Speed Ordering Code Package Name Standard CY7B933-JC CY7B933-JI CY7B933-SC CY7B933-LMB 400 CY7B933-400JC CY7B933-400JI 155 CY7B933-155JC CY7B933-155JI Notes: 29. C1.7 = Transmit Negative K28.5 ( K28.5+) disregarding Current RD. The receiver will only output this Special Character if K28.5 is received with the wrong running disparity. The receiver will output C1.7 if K28.5 is received with RD+, otherwise K28 ...
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... PDF t 9, 10, 11 RISE t 9, 10, 11 FALL t 9, 10, 11 CKR t 9, 10, 11 CPRH t 9, 10, 11 CPRL 10, 11 PRF t 9, 10, 11 PRH 10, 11 ROH 10, 11 CKX t 9, 10, 11 CPXH t 9, 10, 11 CPXL Document #: 38 00189 I 33 CY7B923 CY7B933 ...
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... Package Diagrams 28-Lead Plastic Leaded Chip Carrier J64 28-Square Leadless Chip Carrier L64 MIL-STD-1835 C-4 34 CY7B923 CY7B933 51-85001-A 51-80051 ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOIC S21 CY7B923 CY7B933 51-85026-A ...