CY7C1061AV33-10ZI Cypress Semiconductor Corporation., CY7C1061AV33-10ZI Datasheet

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CY7C1061AV33-10ZI

Manufacturer Part Number
CY7C1061AV33-10ZI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-05256 Rev. *G
Features
Logic Block Diagram
• High speed
• Low active power
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power down when deselected
• TTL compatible inputs and outputs
• Easy memory expansion with CE
• Available in Pb-free and non Pb-free 54-pin TSOP II
— t
— 990 mW (max)
package and non Pb-free 60-ball fine pitch ball grid array
(FBGA) package
AA
= 10 ns
A
A
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
8
9
1
and CE
INPUT BUFFER
DECODER
COLUMN
1M x 16
ARRAY
2
features
198 Champion Court
Functional Description
The CY7C1061AV33 is a high performance CMOS Static RAM
organized as 1,048,576 words by 16 bits.
To write to the device, enable the chip (CE
HIGH) while forcing the Write Enable (WE) input LOW. If Byte
Low Enable (BLE) is LOW, then data from IO pins (IO
IO
(A
from IO pins (IO
specified on the address pins (A
To read from the device, enable the chip by taking CE
and CE
the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is
LOW, then data from the memory location specified by the
address pins will appear on IO
(BHE) is LOW, then data from memory will appear on IO
IO
of Read and Write modes.
The input/output pins (IO
high-impedance state when the device is deselected (CE
HIGH/CE
BHE and BLE are disabled (BHE, BLE HIGH), or a Write
operation is in progress (CE
7
0
15
16-Mbit (1M x 16) Static RAM
), is written into the location specified on the address pins
through A
. See
2
HIGH while forcing the Output Enable (OE) LOW and
2
“Truth Table” on page 7
San Jose
LOW), the outputs are disabled (OE HIGH), the
19
IO
IO
). If Byte High Enable (BHE) is LOW, then data
0
8
8
–IO
–IO
BHE
WE
OE
BLE
through IO
,
7
15
CA 95134-1709
0
1
LOW, CE
through IO
15
0
0
) is written into the location
to IO
through A
CE
CE
for a complete description
CY7C1061AV33
Revised March 26, 2007
2
1
2
7
HIGH, and WE LOW).
. If Byte High Enable
15
) are placed in a
19
1
).
LOW and CE
408-943-2600
0
through
1
LOW
8
to
2
1
[+] Feedback

CY7C1061AV33-10ZI Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-05256 Rev. *G 16-Mbit (1M x 16) Static RAM Functional Description The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, enable the chip (CE HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO ...

Page 2

... IO DNU Notes 1. NC pins are not connected on the die. 2. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper operation. Document #: 38-05256 Rev. *G Commercial Industrial Commercial/Industrial CY7C1061AV33 –10 –12 Unit 275 260 mA 275 260 54-pin TSOP II (Top View BHE ...

Page 3

... CC [ ponents of the test environment. ALL INPUT PULSES 90% 90% 10% 10% Fall time: > 1V/ns (c) to the data retention (V DD CY7C1061AV33 [3] ............................... –0. 0.5V CC Ambient V CC Temperature 3.3V ± 0.3V 0°C to +70°C –40°C to +85°C –10 –12 Unit Max Min Max 2 ...

Page 4

... Read/Write operation is started. power , t are specified with a load capacitance (b) of LZBE LOW (CE HIGH) and WE LOW. Chip enables must be active and WE and byte enables 1 2 and t HZWE CY7C1061AV33 –12 Unit Max Min Max ...

Page 5

... WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE transition LOW and CE 1 Document #: 38-05256 Rev. *G DATA RETENTION MODE 3.0V V > [12, 13 OHA DBE t DOE DATA VALID 50% . CE2 = transition HIGH. 2 CY7C1061AV33 3. DATA VALID HZCE t HZBE t HZOE HIGH IMPEDANCE Page [+] Feedback ...

Page 6

... HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 1 17. During this period, the IOs are in output state and input signals should not be applied. Document #: 38-05256 Rev. *G [15, 16 SCE PWE VALID DATA [15, 16 SCE PWE t SD VALID DATA HZWE . IH CY7C1061AV33 LZWE Page [+] Feedback ...

Page 7

... High-Z Read Lower Bits Only High-Z Data Out Read Upper Bits Only Data In Data In Write All Bits Data In High-Z Write Lower Bits Only High-Z Data In Write Upper Bits Only High-Z High-Z Selected, Outputs Disabled CY7C1061AV33 Mode Power Standby ( Standby ( Active ( Active (I ...

Page 8

... Ordering Information Speed Ordering Code (ns) 10 CY7C1061AV33-10ZXC CY7C1061AV33-10BAC CY7C1061AV33-10ZI CY7C1061AV33-10ZXI CY7C1061AV33-10BAXI 12 CY7C1061AV33-12ZC CY7C1061AV33-12ZXC CY7C1061AV33-12BAC CY7C1061AV33-12ZXI Contact local Cypress representative for availability of the these parts. Package Diagrams Document #: 38-05256 Rev. *G Package Package Type Diagram 51-85160 54-pin TSOP II (Pb-free) 51-85162 60-ball FBGA 51-85160 ...

Page 9

... Cypress against all charges. BOTTOM VIEW A1 CORNER DUMMY BALL (0.3) X12 Ø0. Ø0. Ø0.30±0.05(48X 1.875 A 0.75 0.75 1.00 3.75 6.00 B 8.00±0.10 0.15(4X) CY7C1061AV33 DIMENSIONS IN MM PART # STANDARD PKG. BA60A LEAD FREE PKG. BK60A PKG WEIGHT: 0.30 gms 51-85162-*D Page [+] Feedback ...

Page 10

... Document History Page Document Title: CY7C1061AV33 16-Mbit (1M x 16) Static RAM Document Number: 38-05256 Issue REV. ECN NO. Date ** 113725 03/28/02 *A 117058 07/31/02 *B 117989 08/30/02 *C 120383 11/06/02 *D 124439 2/25/03 *E 492137 See ECN *F 508117 See ECN *G 877322 See ECN Document #: 38-05256 Rev. *G Orig. of Description of Change ...

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