CY7C1357A-100AI Cypress Semiconductor Corporation., CY7C1357A-100AI Datasheet
CY7C1357A-100AI
Related parts for CY7C1357A-100AI
CY7C1357A-100AI Summary of contents
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... The data bus will be in high-impedance state one cycle after chip is deselected or a write cycle is initiated. The CY7C1355A and CY7C1357A have an on-chip 2-bit burst counter. In the burst mode, the CY7C1355A and CY7C1357A provide four cycles of data for a single address presented to the SRAM ...
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... Document #: 38-05265 Rev. *A [1] Address Address Control Control Input Input Registers Registers Control Logic Control Logic Output Buffers Output Buffers [1] Address Control Input Registers Control Logic Output Buffers CY7C1357A CY7C1355A Sel Sel Mux Mux DQa-DQd DQa-DQd Sel Mux DQa, DQb Page ...
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... DQa DQa DQa DQb DQb DQa DQa DQa DQa DQa DQa VSS VSS VSS VSS VCCQ VCCQ VCCQ VCCQ DQa DQa DQa DQa DQa DQa DQa DQa DQa CY7C1357A CY7C1355A 512Kx18—CY7C1357A Top View 100-pin TQFP 100-pin TQFP 100-pin TQFP ...
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... WEN DQd V CLK DQd BWd NC BWa DQd V CEN DQd DQd MODE TMS TDI TCK TDO CY7C1357A CY7C1355A CCQ DQb DQb DQb DQb DQb V CCQ DQb DQb DQb DQb CCQ DQa DQa DQa DQa DQa V CCQ DQa DQa DQa DQa CCQ Page ...
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... When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input. ZZ Input- Sleep Enable: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC. CY7C1357A CY7C1355A Description and sampled HIGH ...
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... V 61, 70, 77 1J, 7J, 1M, 7M, 1U 4A, 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 7R, 1T, 2T, 6T, 6U Pin Descriptions (CY7C1357A) 512K × 18 TQFP Pins Name 37, A0, 36, A1, 32, 33, 34, 35, 44, A 45, 46, 47, 48, 49, 50, 80, 81, 82, 83, 99, 100 93, BWa, ...
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... ADV/ Read or Write operation. The data bus activity for the current cycle takes place one clock cycle later. Input- Clock: This is the clock input to CY7C1357A. Except for OE, ZZ and Clock MODE, all timing references for the device are made with respect to the rising edge of CLK ...
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... CEs must remain inactive for the duration of A...A t after the ZZ input returns LOW. CEN needs to active 00 01 ZZREC before going into the ZZ mode and before you want to come A... back out of the ZZ mode. Fourth Address [5] (internal) A... A... A... A... CY7C1357A CY7C1355A [4] BWb BWc Page [4] ...
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... Ignore Clock Edge/NOP IEEE 1149.1 Serial Boundary Scan (JTAG) Overview This device (except for CY7C1357A) incorporates a serial boundary scan access port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149 ...
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... When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the CY7C1357A CY7C1355A ) SS Page ...
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... When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. CY7C1357A CY7C1355A plus t ). The CS ...
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... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05265 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram CY7C1357A CY7C1355A 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... I = 100 A OHC [23 8.0 mA OLT [23 8.0 mA OHT /2, Undershoot: V (AC)<–0.5V for t<t /2, Power-up KHKH . Control input signals (such as WEN, ADV/LD, etc.) may not have pulse widths less than t CC CY7C1357A CY7C1355A 0 Selection Circuitry [22] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 –30 30 – ...
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... CS CH 27. Test conditions are specified using the load in TAP AC test conditions. Document #: 38-05265 Rev. *A [26, 27] Over the Operating Range Description CY7C1357A CY7C1355A Min. Max. Unit MHz 8 ...
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... Vt = 1.5V 50 TDO (a) GND TEST CLOCK (TCK) TEST MODE SELECT (TMS) TEST DATA IN (TDI) TEST DATA OUT (TDO) Document #: 38-05265 Rev THTL t THTH t t MVTH THMX t DVTH t THDX t TLQV t TLQX CY7C1357A CY7C1355A ALL INPUT PULSES 3.0V 1.5V 1.5 ns 1.5 ns (b) t TLTH Page ...
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... Do not use these instructions; they are reserved for future use. 110 Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. CY7C1357A CY7C1355A Description Description Page ...
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... CY7C1357A CY7C1355A (continued) Signal Name TQFP Bump BWa 93 BWb 94 5G BWc 95 3G BWd 100 DQc 1 2D DQc 2 DQc 3 DQc 6 1G DQc 7 2H DQc 8 1D DQc 9 DQc 12 2G DQc DQd 18 DQd 19 DQd 22 2M DQd 23 1N DQd 24 DQd 25 DQd 28 DQd 29 2N DQd 30 MODE ...
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... Device Deselected DD, 0. > V – 0. DDQ MAX Device deselected; all inputs < > all inputs static max.; CLK frequency = means no input lines are changing. CYC CY7C1357A CY7C1355A Ambient Temperature +70 C 3.3V 5% 2.5–5 to –40°C to +85°C Min. 2 2.0 1.7 –0.3 –0.3 – < V – ...
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... KQHZ KQLZ OEHZ CY7C1357A CY7C1355A Typ. Max 6.5 TQFP Typ ALL INPUT PULSES V 90% CCQ 90% 10% GND 1 V/ns (c) 117 MHz 100 MHz Min ...
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... KQX Q Read BURST READ . Q(A ) represents the first output from the external address etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined 2 is HIGH. 2 CY7C1357A CY7C1355A (Burst Wraps around (CKE# HIGH, eliminates ...
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... D D(A +1) D(A + Write Burst Write ) represents the first input to the external address etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the 2 CY7C1357A CY7C1355A BW (CKE# HIGH, eliminates (Burst Wraps around current L-H clock edge) ...
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... Read DATA In (D) Note: 46. Q(A ) represents the first output from the external address A 1 Document #: 38-05265 Rev BW KQLZ KQX Q Read D Write Write . D(A ) represents the input data to the SRAM corresponding to address CY7C1357A CY7C1355A Q Read ) D Write . 2 Page ...
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... CEN when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal register in the SRAM will retain their previous state. Document #: 38-05265 Rev KQHZ Q KQX D(A 2 CY7C1357A CY7C1355A Q Q Page ...
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... This allows for any pending data transfers (reads or writes completed. Document #: 38-05265 Rev KQHZ Q KQX D D(A ) represents the input data to the SRAM corresponding to address sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High CY7C1357A CY7C1355A OEHZ Q etc. 3 Page ...
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... I/Os are in three-state when exiting ZZ sleep mode. Ordering Information Speed (MHz) Ordering Code 133 CY7C1355A-133AC CY7C1357A-133AC 117 CY7C1355A-117AC CY7C1355A-117AI CY7C1355A-117BGC CY7C1355A-117BGI 100 CY7C1355A-100AC CY7C1357A-100AC CY7C1357A-100AI CY7C1355A-100BGC Document #: 38-05265 Rev ZZS I (active DDZZ Three-state Package Name A101 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack A101 100-lead 14 × ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 Document #: 38-05265 Rev. *A CY7C1357A CY7C1355A 51-85050-A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-lead BGA (14 × 22 × 2.4) BG119 CY7C1357A CY7C1355A 51-85115-*A ...
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... Document Title: CY7C1355A/CY7C1357A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture Document Number: 38-05265 REV ECN Issue Date ** 114118 7/16/02 *A 117837 08/26/02 Document #: 38-05265 Rev. *A Orig. of Change Description of Change KKV New Data Sheet HGK Removed BGA package from 1357A ...