CY7C1370B-167BGC Cypress Semiconductor Corporation., CY7C1370B-167BGC Datasheet
CY7C1370B-167BGC
Related parts for CY7C1370B-167BGC
CY7C1370B-167BGC Summary of contents
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... Write cycle is initiated. The CY7C1370B and CY7C1372B have an on-chip two-bit burst counter. In the burst mode, the CY7C1370B and CY7C1372B provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin ...
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... DQa DPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DPa CY7C1370B CY7C1372B 150 MHz 133 MHz 3.8 4.2 265 245 CY7C1372B (1M × 18) Unit DDQ DPa ...
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... DDQ DQb J V DDQ DQb M V DDQ N DQb 64M U V DDQ Document #: 38-05197 Rev. ** 119-ball Bump BGA CY7C1370B (512K × 36) – 7 × 17 BGA ADV/ DPc DQc V CE ...
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... Pin Configurations (continued) CY7C1370B (512K × 36) – 11 × 15 FBGA DPc NC V DDQ D DQc DQc V DDQ E DQc DQc V DDQ F DQc DQc V DDQ G DQc DQc V DDQ DQd DQd V DDQ K DQd DQd V DDQ L DQd DQd V DDQ ...
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... When left floating MODE will default HIGH interleaved burst order. Power supply inputs to the core of the device. Power supply for the I/O circuitry. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). CY7C1370B CY7C1372B Page ...
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... TCK (BGA only). Serial clock to the JTAG circuit (BGA only). No connects. Reserved for address expansion. Pins are not internally connected. Ground for the device. Should be connected to ground of the system. No connects. Pins are not internally connected. Do not use pins. CY7C1370B CY7C1372B Page ...
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... Write operations. Byte Write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte Write operations. Because the CY7C1370B/CY7C1372B is a common I/O device, data should not be driven into the device while the outputs are active. The OE can be deasserted HIGH before ...
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... X Valid Linear Burst Sequence Fourth First Address Address A[1:0] A[1: CY7C1370B CY7C1372B CLK Comments X X L–H I/Os three-state following next recognized clock. X L–H Clock ignored, all operations suspended. X L–H Address latched. L–H Address latched, data presented two valid clocks later ...
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... Device operation to ZZ ZZS t ZZ recovery time ZZREC [1, 2] Write Cycle Descriptions Function (CY7C1370B) Read Write - No bytes written Write Byte 0 - (DQa and DPa) Write Byte 1 - (DQb and DPb) Write Bytes 1, 0 Write Byte 2 - (DQc and DPc) Write Bytes 2, 0 Write Bytes 2, 1 ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1370B/CY7C1372B incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1–1900, but does not have the set of functions required for full 1149.1 compliance ...
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... TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1370B CY7C1372B Page ...
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... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05197 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1370B CY7C1372B 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- ...
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... Over the Operating Range Test Conditions 100 8 100 A OL GND DDQ /2, Undershoot: V (AC)<0.5V for t<t /2, Power-up TCYC CY7C1370B CY7C1372B 0 Selection Circuitry Min. Max. 2.4 V – 0.2 DD 0.4 0.2 1 0.5 0 <2.6V and V < ...
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... TDOX CY7C1370B CY7C1372B Min. Max Unit ...
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... Do Not Use. This instruction is reserved for future use. Do Not Use. This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1370B CY7C1372B Description Reserved for version number. Defines depth of SRAM. 512K or 1M Defines with of the SRAM. × ...
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... DPd 1P 28 CE3 MODE 3R 29 BWSa BWSb CE2 CE1 DQb CY7C1370B CY7C1372B Signal Bump Signal Name ID Bit # Name 2R 36 DQb 2T 37 DQb 3T 38 DQb DQb 3B 41 DQb 5B 42 DQb 7P 43 DQb ...
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... MHz 6.7-ns cycle, 150 MHz 7.5-ns cycle, 133 MHz Max Device Deselected, All Speeds DD V > < CY7C1370B CY7C1372B Ambient [12] Temperature +70 C 3.3V – +85 C –5% / +10% Min. Max. 3.135 3.63 2.375 3 ...
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... Document #: 38-05197 Rev. ** Test Conditions MHz 3.3V DD DDQ R = 317 V DDQ OUTPUT GND R = 351 INCLUDING JIG AND SCOPE (b) Test Conditions CY7C1370B CY7C1372B Max [15] ALL INPUT PULSES 90% CC 90% 10% < 1V/ns ( (Junction to Ambient) (Junction to Case) 41.54 6.33 44.51 2 ...
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... SRAMs when sharing the same EOLZ CHZ CLZ CY7C1370B CY7C1372B –150 –133 Max. Min. Max. Min. Max. 6.7 7.5 2.3 2.5 2.3 2.5 3 ...
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... CY7C1370B and for CY7C1372B) define a Write cycle and ...
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... CY7C1370B CY7C1372B ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 22. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05197 Rev EOHZ Three-State t EOLZ t ZZS I (active DDZZ Three-state CY7C1370B CY7C1372B t EOV t ZZREC Page ...
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... Ordering Information Speed (MHz) Ordering Code 200 CY7C1370B-200AC CY7C1372B-200AC CY7C1370B-200BGC CY7C1372B-200BGC CY7C1370B-200BZC CY7C1372B-200BZC 167 CY7C1370B-167AC CY7C1372B-167AC CY7C1370B-167BGC CY7C1372B-167BGC CY7C1370B-167BZC CY7C1372B-167BZC 150 CY7C1370B-150AC CY7C1372B-150AC CY7C1370B-150BGC CY7C1372B-150BGC CY7C1370B-150BZC CY7C1372B-150BZC 133 CY7C1370B-133AC CY7C1372B-133AC CY7C1370B-133BGC CY7C1372B-133BGC CY7C1370B-133BZC CY7C1372B-133BZC 167 CY7C1370B-167AI CY7C1372B-167AI CY7C1370B-167BGI CY7C1372B-167BGI CY7C1370B-167BZI CY7C1372B-167BZI ...
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... Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 Document #: 38-05197 Rev. ** CY7C1370B CY7C1372B Page ...
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... Package Diagrams (continued) Document #: 38-05197 Rev. ** 119-ball BGA (14 × 22 × 2.4 mm) CY7C1370B CY7C1372B Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-ball FBGA (13 × 15 × 1.2 mm) BB165A CY7C1370B CY7C1372B Page ...
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... Revision History Document Title: CY7C1370B/CY7C1372B 512K x 36/ Pipelined SRAM with NoBL™ Architecture Document Number: 38-05197 ISSUE REV. ECN NO. DATE ** 112033 12/09/01 Document #: 38-05197 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE DSG Change from Spec number: 38-01070 to 38-05197 CY7C1370B CY7C1372B Page ...