CY7C1373B-100AI Cypress Semiconductor Corporation., CY7C1373B-100AI Datasheet
CY7C1373B-100AI
Related parts for CY7C1373B-100AI
CY7C1373B-100AI Summary of contents
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... Maximum CMOS Standby Current Cypress Semiconductor Corporation Document #: 38-05198 Rev. ** Functional Description The CY7C1371B/CY7C1373B is 3.3V, 512K × 36 and 1M × 18 synchronous flow-thru burst SRAMs, respectively designed to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371B/ CY7C1373B is equipped with the advanced No Bus Latency™ ...
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... DQa DPb 24 57 DQa DDQ 27 54 DDQ DQa DQa DPa 30 51 CY7C1371B CY7C1373B DDQ DPa 74 DQa 73 DQa DDQ DQa 69 DQa ...
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... DQd V CLK SS DQd BWSd NC DQd V CEN SS DQd DPd MODE V DD 64M A A TMS TDI TCK CY7C1373B (1M × 18) – 7 × 17 BGA DDQ CE A ADV/ DQb V CE1 DDQ DQb A BWSb ...
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... DQd DQd V DDQ K DQd DQd V DDQ L DQd DQd V DDQ M DQd DQd V DDQ N DPd NC V DDQ P NC 64M R MODE 32M CY7C1373B (1M × 18) – 11 × 15 FBGA DDQ D NC DQb V DDQ E NC DQb V DDQ F NC DQb V DDQ ...
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... Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). Synchronous Document #: 38-05198 Rev. ** Description and CE to select/deselect the device and CE to select/deselect the device and CE to select/deselect the device during the previous clock rise of the Read cycle. The direction of [X] CY7C1371B CY7C1373B . [31:0] Page ...
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... Document #: 38-05198 Rev. ** Burst Read Access The CY7C1371B/CY7C1373B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above ...
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... DP are automatically three-stated during the data portion of a Write cycle, regardless of the state of OE. Burst Write Access The CY7C1371B/CY7C1373B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the ...
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... Write Bytes 3, 1 Write Bytes Write Bytes 3, 2 Write Bytes Write Bytes Write All Bytes Function (CY7C1373B) Read Write – No Bytes Written Write Byte 0 – (DQa and DPa) Write Byte 1 – (DQb and DPc) Write Both Bytes Document #: 38-05198 Rev. ** considered valid nor is the completion of the operation guaranteed ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1371B/CY7C1373B incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1–1900, but does not have the set of functions required for full 1149.1 compliance ...
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... TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1371B CY7C1373B Page ...
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... The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05198 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1371B CY7C1373B 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- Page ...
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... I 4 100 8 100 A OL GND DDQ /2; undershoot: V (AC) < 0.5V for t < t TCYC IL TCYC CY7C1371B CY7C1373B 0 Selection Circuitry Min. Max. 2.4 V – 0.2 DD 0.4 0.2 1 –0.5 0.7 5 /2; power-up: V < 2.6V and V < 2.4V and V ...
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... TDOV CY7C1371B CY7C1373B Min. Max Unit 100 ...
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... Do Not Use. This instruction is reserved for future use. Do Not Use. This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1371B CY7C1373B Description Bit Size (×36 ...
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... DPd 1P 28 CE3 MODE 3R 29 BWSa BWSb CE2 CE1 DQb CY7C1371B CY7C1373B CY7C1373B (1M × 18) Bump Signal ID Bit # Name Bump DQb DQb DQb DQb DQb DQb ...
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... IN IN DDQ 1/t MAX CYC Max Device Deselected > < CY7C1371B CY7C1373B Ambient [12] Temperature +70 C 3.3V –5% / 2.5V – 5% +10% 3.3V + 10% – +85 C Min. Max. 3.135 3.63 2.375 3. 2.5V 2 ...
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... Document #: 38-05198 Rev. ** Test Conditions MHz 2.5V DD DDQ R = 317 V DDQ OUTPUT 351 INCLUDING JIG AND SCOPE (b) Test Conditions CY7C1371B CY7C1373B Max [16] ALL INPUT PULSES V 90% DD 90% 10% GND < 1V/ns ( (Junction to Ambient) (Junction to Case) 41.54 6 ...
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... SRAMs when sharing the same EOLZ CHZ CLZ CY7C1371B CY7C1373B –100 –83 Min. Max. Min. Max. 10.0 12.0 2.5 3.0 2.5 3.0 8.5 10.0 3 ...
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... CY7C1371B CY7C1373B t t CENH CENS ...
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... CY7C1371B CY7C1373B ...
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... Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 22. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05198 Rev EOHZ Three-state t EOLZ t ZZS I (active DDZZ Three-state CY7C1371B CY7C1373B t EOV t ZZREC Page ...
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... CY7C1371B-117BZC CY7C1373B-117BZC 100 CY7C1371B-100AC CY7C1373B-100AC CY7C1371B-100BGC CY7C1373B-100BGC CY7C1371B-100BZC CY7C1373B-100BZC 83 CY7C1371B-83AC CY7C1373B-83AC CY7C1371B-83BGC CY7C1373B-83BGC CY7C1371B-83BZC CY7C1373B-83BZC 100 CY7C1371B-100AI CY7C1373B-100AI CY7C1371B-100BGI CY7C1373B-100BGI CY7C1371B-100BZI CY7C1373B-100BZI 83 CY7C1371B-83AI CY7C1373B-83AI CY7C1371B-83BGI CY7C1373B-83BGI CY7C1371B-83BZI CY7C1373B-83BZI Shaded areas contain advance information. Document #: 38-05198 Rev. ** Package Name Package Type A101 ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05198 Rev. ** CY7C1371B CY7C1373B 51-85050-A Page ...
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... Package Diagrams (continued) Document #: 38-05198 Rev. ** 119-Lead PBGA ( 2.4 mm) BG119 CY7C1371B CY7C1373B 51-85115-*A Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-Ball FBGA ( 1.2 mm) BB165A CY7C1371B CY7C1373B 51-85122-*B Page ...
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... Revision History Document Title: CY7C1371B/CY7C1373B 512K x 36/ Flow-Thru SRAM with NoBL™ Architecture Document Number: 38-05198 REV. ECN NO. ISSUE DATE ** 112250 03/01/02 Document #: 38-05198 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE DSG Change from Spec number: 38-01071 to 38-05198 CY7C1371B CY7C1373B Page ...