CY7C1380BV25-133AC Cypress Semiconductor Corporation., CY7C1380BV25-133AC Datasheet
CY7C1380BV25-133AC
Related parts for CY7C1380BV25-133AC
CY7C1380BV25-133AC Summary of contents
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... READ cycle. This device also in- corporates pipelined enable circuit for easy depth expansion without penalizing system performance. All inputs and outputs of the CY7C1380BV25 and the CY7C1382BV25 are JEDEC standard JESD8-5 compatible. 200 MHz 3.0 ...
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... REGISTER DQb, DPb Q BYTEWRITE REGISTERS DQa, DPa D Q BYTEWRITE REGISTERS D Q ENABLE CE CE REGISTER D Q ENABLE DELAY REGISTER SLEEP CONTROL 2 CY7C1380BV25 CY7C1382BV25 19 512KX36 MEMORY ARRAY 36 36 OUTPUT INPUT REGISTERS REGISTERS CLK CLK DQ a,b,c MEMORY ARRAY 18 18 OUTPUT INPUT ...
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... DQb 22 DQa 56 DQb DPb SSQ DDQ DQa V 26 SSQ DQa DDQ NC,DQPa CY7C1380BV25 CY7C1382BV25 DDQ 76 V SSQ NC 75 DPa 74 DQa 73 DQa SSQ V 70 DDQ DQa 69 DQa 68 CY7C1382BV25 ...
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... DQb DDQ G NC DQb DDQ DQb M V DDQ N DQb DDQ PRELIMINARY CY7C1380BV25 (512K x 36 ADSP A ADSC DQPc DQc DQc ...
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... LOW, the pins behave as outputs. When HIGH, DQx and DPx are placed in a three-state condition. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA Only). Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA Only). 5 CY7C1380BV25 CY7C1382BV25 CE and 1, 2, are also loaded [1:0] is deasserted HIGH ...
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... Power supply inputs to the core of the device. Should be connected to 3.3V –5% +10% power supply. Ground for the core of the device. Should be connected to ground of the sys- tem. Power supply for the I/O circuitry. Should be connected to a 3.3V –5% +10% power supply. Ground for the I/O circuitry. Should be connected to ground of the system. No Connects. 6 CY7C1380BV25 CY7C1382BV25 ...
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... Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1380BV25/CY7C1382BV25 is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers ...
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... CEs, ADSP , and ADSC must remain inactive for the duration of t after the ZZ input returns LOW. ZZREC Test Conditions Min 0. 0. 0.2V 2t CYC 8 CY7C1380BV25 CY7C1382BV25 Second Third Fourth Address Address Address A A [1:0] [1:0] [1: ...
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... CY7C1380BV25 CY7C1382BV25 ADV OE DQ Write Hi-Z Read ...
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... BWE CY7C1380BV25 CY7C1382BV25 BWc BWb BWa ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1380BV25/CY7C1382BV25 incorporates a serial boundary scan Test Access Port (TAP) in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance ...
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... BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. 12 CY7C1380BV25 CY7C1382BV25 ). The SRAM clock input might not be CH ...
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... Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. PRELIMINARY 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1380BV25 CY7C1382BV25 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- ...
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... TAP Controller [5, 6] Over the Operating Range Test Conditions I = –2 –100 2 100 mA OL GND < V < DDQ /2. Undershoot:V (AC)<0.5V for t<t /2. Power-up TCYC 14 CY7C1380BV25 CY7C1382BV25 0 Selection Circuitry Min. Max. 1.7 2.1 0.7 0.2 1.7 V +0.3 DD –0.3 0.7 –5 5 <2.6V and V <2.4V and V <1.4V for t<200 ms. IH ...
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... Test conditions are specified using the load in TAP AC test conditions. t PRELIMINARY [7, 8] Over the Operating Range Description / ns CY7C1380BV25 CY7C1382BV25 Min. Max. Unit 100 ns 10 MHz ...
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... TAP Timing and Test Conditions 1.25V 50 TDO GND (a) Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO PRELIMINARY 2. TMSS t TMSH t TDIS t TDIH t TDOX 16 CY7C1380BV25 CY7C1382BV25 ALL INPUT PULSES 1.25V t TCYC t TDOV ...
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... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. 17 CY7C1380BV25 CY7C1382BV25 Description Reserved for version number. Defines depth of SRAM. 512K Defines with of the SRAM ...
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... DQd 2N 27 CLK DQd MODE 3R 29 BWa BWb DQb 18 CY7C1380BV25 CY7C1382BV25 Bump Signal Bump ID Bit # Name DQb DQb DQb DQb DQb DQb 2M ...
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... MHz 1/t MAX CYC 6.7-ns cycle, 150 MHz 7.5-ns cycle, 133 MHz Max Device Deselected, All Speeds the temperature CY7C1380BV25 CY7C1382BV25 [ DDQ 2.5V +10%/–5% 2.375V – Min. Max. Unit 3.135 3.6 3.135 3.6 2.375 V DD 1.7 0.7 1.7 – ...
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... Tested initially and after any design or process changes that may affect these parameters. 11. Input waveform should have a slew rate of 1 V/ns. PRELIMINARY Test Conditions MHz 3.3V 2.5V DDQ [11] R=1667 2.5V OUTPUT 2. GND R=1538 R=1538 INCLUDING JIG AND SCOPE (b) 20 CY7C1380BV25 CY7C1382BV25 Max. Unit [10] ALL INPUT PULSES 90% 90% 10% 10% 2.5 ns 2.5 ns (c) ...
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... At any given voltage and temperature, t EOHZ a. PRELIMINARY [12, 13, 14] -200 Min. Max. Min. 5.0 6.0 1.8 2.1 1.8 2.1 1.4 1.5 0.4 0.5 3.0 1.5 1.5 1.4 2.0 0.4 0.5 1.4 2.0 0.4 0.5 1.4 2.0 0.4 0.5 1.4 2.0 0.4 0.5 1.4 2.0 0.4 0.5 1.5 3.0 1 [13, 14] 3.0 [13, 14 [13] 3.5 is less than t and t is less than t . EOLZ CHZ CLZ 21 CY7C1380BV25 CY7C1382BV25 a -166 -150 -133 Max. Min. Max. Min. Max. 6.7 7.5 2.5 3.0 2.5 3.0 1.5 1.5 0.5 0.5 3.4 3.8 4.2 1.5 1.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 3.0 1.5 3.5 1.5 3 3.5 4.0 4 3.5 4.0 4.0 200 mV from ...
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... WE is the combination of BWE, BWx and GW to define a write cycle (see Write Cycle Descriptions table). 16. WDx stands for Write Data to Address X. PRELIMINARY Burst Write ADSP ignored with WD2 masks ADSP UNDEFINED = DON’T CARE 22 CY7C1380BV25 CY7C1382BV25 Pipelined Write Unselected inactive ADSC initiated write WD3 Unselected with CE 2 High ...
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... PRELIMINARY Burst Read ADSP ignored with Suspend Burst ADH masks ADSP OEHZ t DOH CLZ = DON’T CARE = UNDEFINED 23 CY7C1380BV25 CY7C1382BV25 Unselected Pipelined Read inactive 1 ADSC initiated read RD3 Unselected with CHZ ...
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... CO PRELIMINARY Single Write Burst Read ADSP ignored with ADH RD3 masks ADSP EOHZ Out Out In = DON’T CARE = UNDEFINED 24 CY7C1380BV25 CY7C1382BV25 Unselected Pipelined Read inactive DOH Out Out Out t CHZ ...
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... All chip selects need to be active in order to select the device PRELIMINARY CYC CL CH WD1 t ADH t CEH t WES ADSP ignored with CE HIGH Out Out DON’T CARE = UNDEFINED 25 CY7C1380BV25 CY7C1382BV25 WD2 WD3 WD4 t WEH D( DOH t CHZ ...
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... Switching Waveforms (continued) OE Switching Waveforms OE I/Os PRELIMINARY t EOV t EOHZ Three-State t EOLZ 26 CY7C1380BV25 CY7C1382BV25 ...
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... ADSC CE 1 LOW CE 2 HIGH I/Os Note: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. PRELIMINARY t ZZS I (active DDZZ Three-state 27 CY7C1380BV25 CY7C1382BV25 t ZZREC ...
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... Ordering Information Speed (MHz) Ordering Code 200 CY7C1380BV25-200AC 166 CY7C1380BV25-166AC 150 CY7C1380BV25-150AC 133 CY7C1380BV25-133AC 200 CY7C1380BV25-200BGC 166 CY7C1380BV25-166BGC 150 CY7C1380BV25-150BGC 133 CY7C1380BV25-133BGC 200 CY7C1382BV25-200AC 166 CY7C1382BV25-166AC 150 CY7C1382BV25-150AC 133 CY7C1382BV25-133AC 200 CY7C1382BV25-200BGC 166 CY7C1382BV25-166BGC 150 CY7C1382BV25-150BGC 133 CY7C1382BV25-133BGC Shaded areas contain advance information. ...
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... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 PRELIMINARY 29 CY7C1380BV25 CY7C1382BV25 51-85050-A ...
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... Package Diagrams (continued) Revision History Document Title: CY7C1380BV25/CY7C1382BV25 Document Number: 38-01075 REV. ECN NO. ISSUE DATE ** 9/30/2000 *A 3771 05/04/01 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...