CY7C1381B-100AI Cypress Semiconductor Corporation., CY7C1381B-100AI Datasheet
CY7C1381B-100AI
Related parts for CY7C1381B-100AI
CY7C1381B-100AI Summary of contents
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... Read cycle. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. SRAMs integrate All inputs and outputs of the CY7C1381B and the CY7C1383B are JEDEC-standard JESD8-5-compatible. 117 MHz 100 MHz 7.5 8 ...
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... D Q BYTEWRITE REGISTERS D DQc[23:16],DP2 Q BYTEWRITE REGISTERS D DQb[15:8],DP1 Q BYTEWRITE REGISTERS D DQa[7:0],DP0 Q BYTEWRITE REGISTERS D ENABLE Q CE REGISTER CLK SLEEP CONTROL CY7C1381B CY7C1383B 20 1M × 18 MEMORY ARRAY 18 18 INPUT REGISTERS CLK DQ [15:0] DP [1:0] 19 512K × 36 MEMORY ARRAY 36 36 INPUT REGISTERS CLK DQ [31:0] DP ...
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... DQa DQb 23 58 DQa DPb 24 57 DQa DQa VSSQ 26 55 VSSQ VDDQ 27 54 VDDQ DQa DQa DPa CY7C1381B CY7C1383B VDDQ 76 VSSQ DPa 73 DQa 72 DQa 71 VSSQ 70 VDDQ 69 DQa 68 DQa 67 VSS CY7C1383B 66 NC (1M × 18) ...
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... DDQ DDQ DDQ 64M DDQ Document #: 38-05196 Rev. ** 119-ball BGA CY7C1381B (512K × 36 ADSP A A ADSC DQP ...
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... Pin Configurations (continued) CY7C1381B (512K × 36) – 11 × 15 FBGA DPc DQc DQc V E DQc DQc V F DQc DQc V G DQc DQc DQd DQd V K DQd DQd V L DQd DQd V M DQd DQd ...
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... DPa–DPd are placed in a three-state condition. DQ a,b,c and d are eight-bits wide. DP a,b,c and d are one-bit wide. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA only). Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only). CY7C1381B CY7C1383B , ...
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... Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Ground for the I/O circuitry. Should be connected to ground of the system. No connects. Pins are not internally connected. No connects. Reserved for address expansion. Pins are not internally connected. CY7C1381B CY7C1383B Page ...
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... Document #: 38-05196 Rev. ** bytes are written. Bytes not selected during a byte Write operation will remain unaltered. All I/Os are three-stated during a byte Write because the CY7C1381B/CY7C1383B is a common I/O device, the OE must be deasserted HIGH before presenting data to the DQx inputs. Doing so will three-state the output drivers safety precaution, DQx are ...
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... CY7C1381B CY7C1383B Min. Max CYC 2t CYC ADSC ADV ...
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... Write Cycle Description Function (CY7C1381B) Read Read Write Byte 0 – DQa Write Byte 1 – DQb Write Bytes 1, 0 Write Byte 2 – DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes Write Byte 3 – DQd Write Bytes 3, 0 Write Bytes 3, 1 ...
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... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381B/CY7C1383B incorporates a serial boundary scan TAP in the FBGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1–1900, but does not have the set of functions required for full 1149.1 compliance. These ...
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... TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. CY7C1381B CY7C1383B Page ...
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... Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05196 Rev SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1381B CY7C1383B 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- ...
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... Over the Operating Range Test Conditions 100 8 100 A OL GND DDQ / 2; undershoot: V (AC) < 0.5V for t < t TCYC IL TCYC CY7C1381B CY7C1383B 0 Selection Circuitry Min. Max. 2.4 V – 0 0.5 5 /2; power-up: V < 2.6V and V < 2.4V and V ...
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... Test conditions are specified using the load in TAP AC test conditions ns. Document #: 38-05196 Rev. ** [7, 8] Over the Operating Range Description CY7C1381B CY7C1383B Min. Max Unit 100 ns 10 MHz ...
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... TDOV TDOX CY7C1381B CY7C1383B 1.50V t TCYC ...
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... Do Not Use. This instruction is reserved for future use. Do Not Use. This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. CY7C1381B CY7C1383B Description Reserved for version number. Defines depth of SRAM. 512K or 1M Defines with of the SRAM. × ...
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... CLK DQd MODE 3R 29 BWa BWb CE DQb CY7C1381B CY7C1383B Signal Bump Signal Name ID Bit # Name 2R 36 DQb 2T 37 DQb 3T 38 DQb DQb 3B 41 DQb 5B 42 DQb 7P 43 DQb ...
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... MHz V > V – 0.3V IN DDQ 1/t 12-ns cycle, 83 MHz MAX CYC Max Device All speeds DD Deselected, V > < CY7C1381B CY7C1383B Ambient [10] Temp V DD 0°C to +70°C 3.3V 2.5V – 5% –5% / +10% 3.3V + 10% –40°C to +85°C Min. Max. 3.135 3.63 2.375 3.63 = 2.5V 2.0 = 3.3V 2.4 = 2.5V 0 ...
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... Input waveform should have a slew rate of 1 V/ns. Document #: 38-05196 Rev. ** Test Conditions MHz 3.3V 3.3V DDQ R = 1667 V DDQ OUTPUT 1538 INCLUDING JIG AND SCOPE (b) Test Conditions CY7C1381B CY7C1383B Max [12] ALL INPUT PULSES V DD 90% 10% GND < 1V/ns ( (Junction to Ambient) (Junction to Case) 41.54 6.33 44 ...
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... CHZ CLZ OEV EOLZ EOHZ voltage. 15. At any given voltage and temperature, t EOHZ Document #: 38-05196 Rev. ** [13, 14, 15] –117 Min. Max. 8.5 2.3 2.3 1.5 0.5 7.5 1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.0 1.3 [13, 14] 4.0 [13, 14] 0 [13] 3.4 is less than t and t is less than t . EOLZ CHZ CLZ CY7C1381B CY7C1383B –100 –83 Min. Max. Min. Max. Unit 10.0 12.0 2.5 3.0 2.5 3.0 1.5 1.5 0.5 0.5 8.5 10.0 1.5 1.5 1.5 1.5 0.5 0.5 1.5 1.5 0.5 0.5 1.5 1.5 0.5 0.5 1.5 1.5 0.5 0.5 1.5 1.5 0.5 0.5 3.0 3.0 1 ...
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... CY7C1381B CY7C1383B Pipelined Write Unselected ...
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... CY7C1381B CY7C1383B Unselected Pipelined Read inactive ...
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... CY7C1381B CY7C1383B ...
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... CY7C1381B CY7C1383B ...
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... OE Switching Waveforms ZZ Mode Timing [19, 21] CLK ADSP HIGH ADSC CE 1 LOW CE 2 HIGH I/Os Note: 21. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05196 Rev EOHZ Three-State I/Os t EOLZ t ZZS I (active CCZZ Three-state CY7C1381B CY7C1383B t EOV t ZZREC Page ...
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... CY7C1383B-117BGC CY7C1381B-117BZC CY7C1383B-117BZC 100 CY7C1381B-100AC CY7C1383B-100AC CY7C1381B-100BGC CY7C1383B-100BGC CY7C1381B-100BZC CY7C1383B-100BZC 83 CY7C1381B-83AC CY7C1383B-83AC CY7C1381B-83BGC CY7C1383B-83BGC CY7C1381B-83BZC CY7C1383B-83BZC 100 CY7C1381B-100AI CY7C1383B-100AI CY7C1381B-100BGI CY7C1383B-100BGI CY7C1381B-100BZI CY7C1383B-100BZI 83 CY7C1381B-83AI CY7C1383B-83AI CY7C1381B-83BGI CY7C1383B-83BGI CY7C1381B-83BZI CY7C1383B-83BZI Shaded areas contain advance information. Document #: 38-05196 Rev. ** Package Name Package Type ...
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... Pin Configurations 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 Document #: 38-05196 Rev. ** CY7C1381B CY7C1383B Page ...
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... Pin Configurations (continued) Document #: 38-05196 Rev. ** 119-lead FBGA (14 × 22 × 2.4 mm) BG119 CY7C1381B CY7C1383B Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 165-ball FBGA (13 × 15 × 1.2 mm) BB165A CY7C1381B CY7C1383B Page ...
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... Revision History Document Title: CY7C1381B/CY7C1383B 512K x36/1M x18 Flow-Thru SRAM Document Number: 38-05196 ISSUE REV. ECN NO. DATE ** 112032 12/09/01 Document #: 38-05196 Rev. ** ORIG. OF CHANGE DESCRIPTION OF CHANGE DSG Change from Spec number: 38-01077 to 38-05196 CY7C1381B CY7C1383B Page ...