CY7C1383C-117AC Cypress Semiconductor Corporation., CY7C1383C-117AC Datasheet
CY7C1383C-117AC
Related parts for CY7C1383C-117AC
CY7C1383C-117AC Summary of contents
Page 1
... TQFP and 165 fBGA package only. 119 BGA is offered only in 1 Chip Enable Cypress Semiconductor Corporation Document #: 38-05238 Rev. *B Functional Description The CY7C1381C/CY7C1383C is a 3.3V, 512K x 36 and Synchronous Flowthrough SRAMs, respectively designed to interface with high-speed microprocessors with minimum ) DD glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version) ...
Page 2
... DQ DQP , A CEN BW A BYTE BWE WRITE REGISTER GW ENABLE CE1 REGISTER CE2 CE3 OE ADV/LD SLEEP ZZ CONTROL Logic Block Diagram – CY7C1383C (1M x 18) ADDRESS A0,A1,A REGISTER WE MODE ADV CLK OE CE1 CE2 ADSC CE3 ADSP ZZ DQ ,DQP B B WRITE REGISTER ,DQP ...
Page 3
... DDQ V 76 SSQ NC 75 DQP SSQ V 70 DDQ CY7C1383C ( DDQ V 60 SSQ SSQ V 54 ...
Page 4
... BWE DQP MODE TMS TDI TCK CY7C1383C ( ADSP A A ADSC ADV ...
Page 5
... TDI TMS CY7C1383C ( CLK ...
Page 6
... F4 B8 Input- Asynchronous G4 A9 Input- Synchronous A4 B9 Input- Synchronous CY7C1381C CY7C1383C Description Address Inputs used to select one of the 512K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is [2] active LOW, and and sampled active. A feed the 2-bit counter. ...
Page 7
... Input-Static D4,D8,E4, Power Supply Power supply inputs to the core of the E8,F4,F8, G4,G8,H4, H8,J4,J8, K4,K8,L4, L8,M4,M8 CY7C1381C CY7C1383C Description Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A are also loaded into the burst [1:0] counter ...
Page 8
... H10,N2,N5,N7, N10,P1,P2, Ground/DNU This pin can be connected to Ground or CY7C1381C CY7C1383C Description Power supply for the I/O circuitry. Ground for the core of the device. Ground for the I/O circuitry. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be left unconnected ...
Page 9
... CY7C1383C:Pin Definitions TQFP BGA (3-Chip (1-Chip Name Enable) Enable 37,36,32,33,34, P4,N4,A2,B2 35,42,43,44,45, C2,R2,T2,A3, 46,47,48,49,50, B3,C3,T3,A5, 80,81,82,99,100 B5,C5,T5,A6, B6,C6,R6,T6 93,94 L5, BWE CLK [ ADV Document #: 38-05238 Rev. *B fBGA (3-Chip Enable) I/O R6,P6,A2, Input- A10,A11,B2, Synchronous B10,N6,P3,P4, P8,P9,P10, P11,R3,R4, R8,R9,R10,R11 B5,A4 Input- Synchronous H4 B7 ...
Page 10
... CY7C1383C:Pin Definitions (continued) TQFP BGA (3-Chip (1-Chip Name Enable) Enable) 84 ADSP 85 ADSC ZZ 64 58,59,62,63,68, P7,K7,G7,E7, 69,72,73,8,9,12, ,H6,L6,N6,D1,H 13, 1,L1,N1,E2,G2, 18,19,22,23 K2,M2 74,24 D6,P2 DQP [A:B] MODE 31 Document #: 38-05238 Rev. *B fBGA (3-Chip Enable) I Input- Synchronous B4 A8 Input- Synchronous T7 H11 Input- Asynchronous J10,K10, I/O- L10,M10, Synchronous D11,E11, F11,G11,J1,K1, L1,M1, D2,E2,F2, G2 C11,N1 I/O- Synchronous R3 R1 Input-Static CY7C1381C ...
Page 11
... CY7C1383C:Pin Definitions (continued) TQFP BGA (3-Chip (1-Chip Name Enable) Enable) V 15,41,65,91 C4,J2,J4,J6, 4,11,20,27, A1,A7,F1,F7,J1, DDQ 54,61,70,77 J7,M1,M7,U1,U V 17,40,67,90 D3,D5,E3,E5,F3 SS ,F5,G5,H3, H5,K3,K5,L3,M3 M5,N3, N5,P3,P5 V 5,10,21,26, SSQ 55,60,71,76, TDO - TDI - TMS - TCK - Document #: 38-05238 Rev. *B fBGA (3-Chip Enable) I/O D4,D8,E4, Power Supply Power supply inputs to the core of the E8,F4,F8, G4,G8, H4,H8,J4, J8,K4,K8, L4,L8,M4, M8 C3,C9,D3, I/O Power D9,E3,E9, Supply 7 F3,F9,G3, G9,J3,J9, K3,K9,L3, L9,M3,M9, N3,N9 C4,C5,C6, Ground C7,C8,D5, D6,D7,E5, , E6,E7,F5, F6,F7,G5, G6,G7,H1, H2,H5,H6, H7,J5,J6,J7,K5, K6,K7,L5,L6,L7, M5, M6,M7,N4 I/O Ground U5 P7 JTAG serial output ...
Page 12
... CY7C1383C:Pin Definitions (continued) TQFP BGA (3-Chip (1-Chip Name Enable) Enable) NC 1,2,3,6,7,16,25, B1,B7,C1,C7,D 28,29,30,38,39, 2,D4,D7,E1,E6, 51,52,53,56,57, H2,F2,G1,G6,H 66,75,78,79,95, 7,J3,J5,K1,K6,L 96 4,L2,L7,M6,N2, N7,L7,P1,P6,R1 ,R5,R7,T1,T4,U V /DNU 14 SS Document #: 38-05238 Rev. *B fBGA (3-Chip Enable) I/O A1,A5,B1, - B4,B11,C1,C2,C 10,D1,D10,E1,E 10,F1,F10,G1,G 10,H3,H9,H10,J 2,J11,K2,K11, L2,L11,M2,M11, 6 N2,N5,N7,N10, N11,P1,P2, Ground/DNU CY7C1381C CY7C1383C Description No Connects. Not internally connected to the die. 36M, 72M, 144M and 288M are address expansion pins are not internally connected to the die ...
Page 13
... Maximum access delay from the clock rise ( 6.5 ns (133-MHz device). C0 The CY7C1381C/CY7C1383C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium processors. The linear burst sequence is suited for processors that utilize a linear burst sequence ...
Page 14
... CY7C1381C CY7C1383C Min. Max. Unit CYC 2t ns CYC 2t ns CYC 0 ns ADV WRITE OE CLK L-H Tri-State L-H Tri-State L-H Tri-State ...
Page 15
... DQP , DQP ) B A Write All Bytes Write All Bytes Note: 8. Table only lists a partial listing of the byte write combinations. Any Combination of BW [3] Truth Table for Read/Write Function (CY7C1383C) Read Read Write Byte and DQP ) A A Write Byte and DQP ) ...
Page 16
... Truth Table for Read/Write Function (CY7C1383C) Write All Bytes Document #: 38-05238 Rev. *B BWE CY7C1381C CY7C1383C Page ...
Page 17
... IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1381C/CY7C1383C incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM ...
Page 18
... TAP controller’s capture setup plus hold time (t plus The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a portion of SAMPLE/PRELOAD instruction. If this is an issue still CY7C1381C CY7C1383C Unlike the SAMPLE/PRELOAD ). Page ...
Page 19
... These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing CYC TL t TMSS t TMSH t TDIS t TDIH DON’T CARE /t = 1ns R F CY7C1381C CY7C1383C TDOV t TDOX UNDEFINED [9, 10] Symbol Min Max t 100 TCYC ...
Page 20
... V = 3.3V = -100 µA DDQ 2.5V DDQ 8.0 mA DDQ 8 2.5V OL DDQ I = 100 µ 3.3V OL DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ V = 3.3V DDQ V = 2.5V DDQ GND < V < DDQ CY7C1381C CY7C1383C V to 2.5V SS 1.25V 20pF O MIN MAX UNITS 2.4 V 2.0 V 2.9 V 2.1 V 0.4 V 0.4 V 0.2 V 0 -0.3 0.8 V -0.3 0 µA ...
Page 21
... Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. CY7C1381C CY7C1383C DESCRIPTION Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor ...
Page 22
... Not Bonded (Preset Internal Internal CY7C1381C CY7C1383C Page ...
Page 23
... BGA Boundary Scan Order CY7C1383C (1M x 18) BIT BALL Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset ...
Page 24
... Not Bonded (Preset CY7C1381C CY7C1383C Page ...
Page 25
... Not Bonded (Preset Not Bonded (Preset R11 30 R10 P10 P11 Document #: 38-05238 Rev. *B CY7C1383C (1M x 18) BIT# BALL Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset Not Bonded (Preset ...
Page 26
... inputs static /2), undershoot: V (AC) > -2V (Pulse width less than t CYC IL (min.) within 200ms. During this time V < CY7C1381C CY7C1383C Ambient Temperature V DD 0°C to +70°C 3.3V– 5%/+10% 2.5V – 5% -40°C to +85°C Min. Max. 3.135 3.6 3.135 ...
Page 27
... MHz 3.3V 2.5V DDQ R = 317: 3.3V OUTPUT 351: INCLUDING JIG AND (b) SCOPE R = 1667: 2.5V OUTPUT =1538: INCLUDING JIG AND (b) SCOPE CY7C1381C CY7C1383C TQFP BGA fBGA Package Package Package TQFP BGA fBGA Package Package Package ...
Page 28
... V POWER is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same OELZ CHZ CLZ = 2.5V. DDQ CY7C1381C CY7C1383C 117 MHz 100 MHz Min. Max. Min. Max 8.5 10 2.3 2 ...
Page 29
... CDV Single READ Document #: 38-05238 Rev ADS t ADH ADVH ADVS ADV suspends burst t CDV t OELZ t OEHZ t DOH Q(A2 DON’T CARE CY7C1381C CY7C1383C Deselect Cycle Q( Q(A2) Q( Burst wraps around to its initial state BURST READ UNDEFINED Page CHZ Q( ...
Page 30
... OEHZ Data Out (Q) BURST READ Single WRITE Document #: 38-05238 Rev. *B ADSC extends burst WES WEH ADV suspends burst D(A2 BURST WRITE DON’T CARE UNDEFINED CY7C1381C CY7C1383C t ADS t ADH A3 t WES t WEH t ADVS t ADVH D( D(A3 Extended BURST WRITE Page ...
Page 31
... Document #: 38-05238 Rev WES WEH OELZ D(A3) t OEHZ t CDV Q(A4) Single WRITE DON’T CARE is HIGH and CE is LOW. When CE is HIGH LOW. X CY7C1381C CY7C1383C A5 D(A5) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back BURST READ WRITEs UNDEFINED is HIGH LOW HIGH Page D(A6) ...
Page 32
... SUPPLY ALL INPUTS (except ZZ) Outputs (Q) Ordering Information Speed (MHz) Ordering Code 133 CY7C1381C-133AC CY7C1383C-133AC CY7C1381C-133BGC CY7C1383C-133BGC CY7C1381C-133BZC CY7C1383C-133BZC 117 CY7C1381C-117AC CY7C1383C-117AC CY7C1381C-117BGC CY7C1383C-117BGC CY7C1381C-117BZC CY7C1383C-117BZC CY7C1381C-117AI CY7C1383C-117AI CY7C1381C-117BGI CY7C1383C-117BGI CY7C1381C-117BZI CY7C1383C-117BZI Document #: 38-05238 Rev ZZI I DDZZ High-Z DON’T CARE ...
Page 33
... CY7C1381C-100AC CY7C1383C-100AC CY7C1381C-100BGC CY7C1383C-100BGC CY7C1381C-100BZC CY7C1383C-100BZC CY7C1381C-100AI CY7C1383C-100AI CY7C1381C-100BGI CY7C1383C-100BGI CY7C1381C-100BZI CY7C1383C-100BZI Shaded areas contain advance information. Please contact your local sales representative for availability of these parts. Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 16.00±0.20 14.00±0.10 100 0.08 MIN. 0° ...
Page 34
... Package Diagrams (continued) Document #: 38-05238 Rev. *B CY7C1381C CY7C1383C 51-85115-*B Page ...
Page 35
... Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05238 Rev. *B 165-Ball FBGA ( 1.2 mm) BB165A CY7C1381C CY7C1383C 51-85122-*C Page ...
Page 36
... Document History Page Document Title: CY7C1381C/CY7C1383C 18-Mb (512K x 36/1M x 18) Flow-Through SRAM Document Number: 38-05238 REV. ECN NO. Issue Date ** 116278 08/27/02 *A 121541 11/21/02 *B 206081 See ECN Document #: 38-05238 Rev. *B Orig. of Change Description of Change SKX New Data Sheet DSG Updated package diagrams 51-85115 (BG119) to rev. *B and 51-85122 (BB165A) to rev ...