CY7C1512-25SC Cypress Semiconductor Corporation., CY7C1512-25SC Datasheet

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CY7C1512-25SC

Manufacturer Part Number
CY7C1512-25SC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Functional Description
The CY7C1512 is a high-performance CMOS static RAM or-
ganized as 65,536 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
HIGH chip enable (CE
Selection Guide
Cypress Semiconductor Corporation
CE
CE
WE
OE
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum CMOS
Standby Current (mA)
• High speed
• CMOS for optimum speed/power
• Low active power
• Low standby power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
1
2
— t
— 770 mW
— 28 mW
A
A
A
A
A
A
A
A
0
1
2
3
4
5
6
7
AA
Logic Block Diagram
= 15 ns
INPUT BUFFER
2
DECODER
64K x 8
COLUMN
ARRAY
), an active LOW output enable (OE),
Commercial
Commercial
POWER
DOWN
1
, CE
2
, and OE options
3901 North First Street
1
7C1512-15
), an active
PRELIMINARY
140
15
5
1512-1
7C1512-20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
and three-state drivers. This device has an automatic pow-
er-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
two (CE
I/O
pins (A
Reading from the device is accomplished by taking chip en-
able one (CE
write enable (WE) and chip enable two (CE
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH or CE
during a write operation (CE
The CY7C1512 is available in standard TSOP type I and
450-mil-wide plastic SOIC packages.
0
1
2
3
4
5
6
7
130
7
20
) is then written into the location specified on the address
5
CE
V
WE
A
A
A
A
A
NC
NC
A
A
CC
A
A
A
A
0
13
15
14
12
11
9
8
2
7
6
5
4
2
1
through A
) input HIGH. Data on the eight I/O pins (I/O
) and write enable (WE) inputs LOW and chip enable
San Jose
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
LOW), the outputs are disabled (OE HIGH), or
) and output enable (OE) LOW while forcing
7C1512-25
15
120
25
5
).
Pin Configurations
GND
64K x 8 Static RAM
I/O
I/O
I/O
A
A
NC
NC
A
A
A
A
A
A
A
A
14
12
7
6
5
4
3
2
1
0
0
1
2
June 1996 – Revised October 1996
(not to scale)
1
Top View
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
Top View
CA 95134
LOW, CE
TSOP I
SOIC
0
7C1512-35
through I/O
110
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
35
5
2
HIGH, and WE LOW).
CE
A
CE
I/O
I/O
I/O
I/O
I/O
V
A
WE
A
A
A
A
OE
10
CC
15
13
8
9
11
7
6
5
4
3
2
1
CY7C1512
7
) are placed in a
2
) HIGH. Under
408-943-2600
7C1512-70
110
0
70
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
5
through
1512-2
OE
A
CE
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
10
0
1
2
3
7
6
5
4
3
2
1
0
1
1

Related parts for CY7C1512-25SC

CY7C1512-25SC Summary of contents

Page 1

... I/O pins. , and OE options 2 The eight input/output pins (I/O high-impedance state when the device is deselected (CE HIGH or CE LOW), the outputs are disabled (OE HIGH during a write operation (CE The CY7C1512 is available in standard TSOP type I and ), an active 1 450-mil-wide plastic SOIC packages. I/O 0 I/O 1 I/O ...

Page 2

... > < MAX Max > V – 0.3V < 0.3V, V > V – 0.3V < 0.3V, f CY7C1512 Ambient [2] Temperature + – + 7C1512-15 7C1512-20 7C1512-25 Min. Max. Min. Max. Min. Max. 2.4 2.4 2.4 0.4 0.4 0 2.2 ...

Page 3

... HIGH to Write End less than less than t HZCE LZCE HZOE LZOE LOW, CE HIGH, and WE LOW CY7C1512 Max ALL INPUT PULSES 90% 10% <3ns 7C1512-20 7C1512-25 Max. Min. Max. Min. Max ...

Page 4

... HIGH to Data Valid 2 [8] HIGH to Low Z 2 [7, 8] LOW to High Z 2 HIGH to Power-Up 2 LOW to Power-Down 2 HIGH to Write End OHA = CY7C1512 7C1512-35 7C1512-70 Min. Min. Min. Min. Unit ...

Page 5

... LOW simultaneously with WE going HIGH, the output remains in a high-impedance state PRELIMINARY DOE DATA VALID 50% [13, 14 SCE SCE DATA VALID transition LOW and CE transition HIGH CY7C1512 t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB 1512 1512-7 ...

Page 6

... During this period the I/Os are in the output state and input signals should not be applied. PRELIMINARY [13, 14 SCE t SCE PWE t SD DATA VALID IN [14 SCE t SCE PWE t SD DATA VALID 6 CY7C1512 1512 LZWE 1512-9 ...

Page 7

... L Data High Z Ordering Information Speed Package (ns) Ordering Code 15 CY7C1512-15SC CY7C1512-15ZC CY7C1512-20ZI 20 CY7C1512-20SC CY7C1512-20ZC CY7C1512-20ZI 25 CY7C1512-25SC CY7C1512-25ZC CY7C1512-25ZI 35 CY7C1512-35SC 70 CY7C1512-70SC CY7C1512-70ZC CY7C1512-70ZI Shaded areas contain advanced information. Document #: 38-00522-A PRELIMINARY Mode Power-Down Standby (I Power-Down Standby (I Read Active (I Write Active (I Selected, Outputs Disabled ...

Page 8

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 32-Lead (450 -Mil) Molded SOIC S34 32-Lead Thin Small Outline Package Z32 CY7C1512 ...

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