CY7C374I-83YMB Cypress Semiconductor Corporation., CY7C374I-83YMB Datasheet
CY7C374I-83YMB
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CY7C374I-83YMB Summary of contents
Page 1
... F often allows users to change existing logic designs while si- multaneously fixing pinout assignments. The 128 macrocells in the CY7C374i are divided between eight logic blocks. Each logic block includes 16 macrocells product term array, and an intelligent product term allocator ...
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... I/O I I/O 11 I/O V I/O ISR I/O I/O I/O I/O I/O I/O GND I/O I/O I/O I/O I GND CY7C374i GND I/O /SDI 54 71 I I/O 48 CLK / GND CCIO CLK / I I/O ...
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... CY7C374i 75 SDI 74 V CCIO I CLK / GND CCIO CLK ...
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... PIM regardless of its configuration. Programmable Interconnect Matrix The Programmable Interconnect Matrix (PIM) connects the eight logic blocks on the CY7C374i to the inputs and to each other. All inputs (including feedbacks) travel through the PIM. There is no speed penalty incurred by signals traversing the PIM ...
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... Com’l “L” – Military V = Min 0. Min 2. Max Max CCINT 5 CY7C374i Ambient V CC Temperature V V CCINT + .25V .5V 5V 3.3V –55° +125° .5V Min. Typ. Max. [5] 2 ...
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... INCLUDING JIG AND SCOPE (b) 7C374i-5 Output Waveform Measurement Level V OH –0.5V –0. –0. –0.5V EN measured with 35-pF AC Test Load CY7C374i Min. Max 84-Lead 84-Lead PLCC CLCC Max. Unit 100 Cycles ALL INPUT PULSES 3.0V 90% 10% GND <2ns ( Max ...
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... All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load. 15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C374i. This specification is met for the devices operating at the same ambient temperature and at the same power supply voltage. ...
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... PDL 8 CY7C374i 7C374i–66 7C374i–83 7C374iL–66 Max. Min. Max. Min. Max 500 500 7C374i 7C374i-8 ...
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... OUTPUT LATCH ENABLE Latched Input and Output LATCHED INPUT LATCHED OUTPUT INPUT LATCH ENABLE OUTPUT LATCH ENABLE LATCH ENABLE ICO PDL ICOL t ICS CY7C374i ICO PDLL 7C374i-10 7C374i-11 7C374i-12 ...
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... Switching Waveforms (continued) Asynchronous Reset INPUT REGISTERED OUTPUT CLOCK Asynchronous Preset INPUT REGISTERED OUTPUT CLOCK Output Enable/Disable INPUT OUTPUTS CY7C374i 7C374i-13 7C374i-14 7C374i-16 ...
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... CY7C374i–100AC CY7C374i–100JC 83 CY7C374i–83AC CY7C374i–83JC CY7C374i–83AI CY7C374i–83JI CY7C374i-83GMB CY7C374i–83YMB 66 CY7C374i–66AC CY7C374i–66JC CY7C374i–66AI CY7C374i–66JI CY7C374i-66GMB CY7C374i–66YMB CY7C374iL–66AC CY7C374iL–66JC MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups ...
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... Package Diagrams 100-Pin Thin Quad Flat Pack A100 84-Pin Grid Array (Cavity Up) G84 12 CY7C374i ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 84-Lead Plastic Leaded Chip Carrier J83 84-Pin Ceramic Leaded Chip Carrier Y84 CY7C374i ...