ID80C86-2 Intersil Corporation, ID80C86-2 Datasheet
ID80C86-2
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ID80C86-2 Summary of contents
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TM August 22, 2006 Features • Compatible with NMOS 8086 • Completely Static CMOS Design - ...
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Functional Diagram EXECUTION UNIT REGISTER FILE DATA POINTER AND INDEX REGS (8 WORDS) 16-BIT ALU FLAGS TEST INTR NMI RQ/GT0 HOLD HLDA CLK MEMORY INTERFACE BUS INTERFACE UNIT EXECUTION UNIT 80C86 BUS INTERFACE UNIT RELOCATION REGISTER FILE SEGMENT ...
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Pin Description The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers). PIN ...
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Pin Description (Continued) The following pin function descriptions are for 80C86 systems in either minimum or maximum mode. The “Local Bus” in these description is the direct multiplexed bus interface connection to the 80C86 (without regard to additional bus buffers). ...
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Minimum Mode System (Continued) The following pin function descriptions are for the 80C86 in minimum mode (i.e., MN/ minimum mode are described; all other pin functions are as described below. PIN SYMBOL NUMBER TYPE DT DEN ...
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Maximum Mode System (Continued) The following pin function descriptions are for the 80C86 system in maximum mode (i.e., MN/MX - GND). Only the pin functions which are unique to maximum mode are described below. PIN SYMBOL NUMBER TYPE RQ/GT0 31, ...
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Functional Description Static Operation All 80C86 circuitry is of static design. Internal registers, counters and latches are static and require no refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microproces- sors. The ...
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Except for the performance penalty, this double access is transpar- ent to the software. The performance penalty does ...
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Status bits S3 through S7 are time multiplexed with high order address bits and the BHE signal, and are therefore valid during T2 through T4. S3 and S4 indicate which seg- ment register (see Instruction Set Description) was used for ...
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NWAIT) = TCY T1 T2 CLK ALE S2-S0 BHE, ADDR/ A19-A16 STATUS BUS RESERVED A15-A0 ADDR/DATA RD, INTA READY WAIT DT/R DEN MEMORY ACCESS TIME WR 80C86 T3 TWAIT BHE S7-S3 A19-A16 FOR DATA IN ...
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External Interface Processor RESET and Initialization Processor initialization or start up is accomplished with activa- tion (HIGH) of the RESET pin. The 80C86 RESET is required to be HIGH for greater than 4 CLK cycles. The 80C86 will termi- nate ...
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During the response sequence (Figure 5) the processor exe- cutes two successive (back-to-back) interrupt acknowledge cycles. The 80C86 emits the LOCK signal (Max mode only) from T2 of the first bus cycle until T2 of the second. A local bus ...
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The read control signal is also asserted at T2. The read (RD) signal causes the addressed device to enable its data bus drivers to the local bus. ...
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Bus Timing - Medium Size Systems For medium complexity systems the MN/MX pin is con- nected to GND and the 82C88 Bus Controller is added to the system as well as an 82C82/82C83 latch for latching the system address, and ...
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V CC MN/MX CLK 82C84A/85 S0 CLOCK READY S1 GENERATOR/ RESET RES S2 RDY 80C86 CPU LOCK WAIT GND STATE GENERATOR GND AD0-AD15 1 A16-A19 BHE GND 0.1μF ...
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DC Electrical Specifications SYMBOL PARAMETER V Logical Zero Input Voltage IL V CLK Logical One Input Voltage IHC V Logical Zero Input Voltage CLK ILC V Output High Voltage OH V Output ...
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AC Electrical Specifications MINIMUM COMPLEXITY SYSTEM SYMBOL PARAMETER (6) TDVCL Data In Setup Time (7) TCLDX1 Data In Hold Time (8) TR1VCL RDY Setup Time into 82C84A (Notes 7, 8) (9) TCLR1X ...
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AC Electrical Specifications MINIMUM COMPLEXITY SYSTEM SYMBOL PARAMETER (31) TCVCTX Control Inactive Delay (32) TAZRL Address Float to READ Active (33) TCLRL RD Active Delay (34) TCLRH RD Inactive Delay (35) TRHAV ...
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Waveforms CLK (82C84A OUTPUT) (30) TCHCTV M/IO (17) TCLAV BHE/S7, A19/S6-A16/S3 (23) TCLLH ALE RDY (82C84A INPUT) SEE NOTE READY (80C86 INPUT) AD15-AD0 RD READ CYCLE (WR, INTA = DT/R DEN FIGURE 7A. BUS TIMING - MINIMUM ...
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Waveforms (Continued) CLK (82C84A OUTPUT) (17) TCLAV AD15-AD0 WRITE CYCLE DEN (RD, INTA, DT (19) TCLAZ AD15-AD0 DT/R INTA CYCLE (SEE NOTE) (RD INTA BHE = DEN SOFTWARE ...
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AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) TIMING REQUIREMENTS SYMBOL PARAMETER (1) TCLCL CLK Cycle Period (2) TCLCH CLK Low Time (3) TCHCL CLK High Time (4) TCH1CH2 CLK ...
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AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) TIMING REQUIREMENTS SYMBOL PARAMETER (23) TCLAV Address Valid Delay (24) TCLAX Address Hold Time (25) TCLAZ Address Float Delay (26) TCHSZ Status ...
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AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) TIMING REQUIREMENTS SYMBOL PARAMETER (35) TCVNV Control Active Delay (Note 10) (36) TCVNX Control Inactive Delay (Note 10) (37) TAZRL Address Float ...
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Waveforms CLK TCLAV QS0, QS1 (21) TCHSV S2, S1, S0 (EXCEPT HALT) (23) TCLAV BHE/S7, A19/S6-A16/S3 TSVLH (27) TCLLH ALE (82C88 OUTPUT) NOTE RDY (82C84 INPUT) READY 80C86 INPUT) READ CYCLE TCLAV AD15-AD0 RD (41) TCHDTL DT/R 82C88 OUTPUTS MRDC ...
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Waveforms (Continued) CLK TCHSV (21) S2, S1, S0 (EXCEPT HALT) WRITE CYCLE AD - DEN 82C88 OUTPUTS SEE NOTES AMWC OR AIOWC 18, 19 MWTC OR IOWC INTA CYCLE AD15-AD0 (SEE NOTES 21, 22) (25) TCLAZ AD15-AD0 (28) ...
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Waveforms (Continued) CLK TCLGH (44) (1) TCLCL RQ/GT PREVIOUS GRANT AD15-AD0 RD, LOCK BHE/S7, A19/S0-A16/S3 S2, S1, S0 NOTE: The coprocessor may not drive the busses outside the region shown without risking contention. FIGURE 9. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ...
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Waveforms (Continued) AC Test Circuit OUTPUT FROM DEVICE UNDER TEST NOTE: Includes stay and jig capacitance. AC Testing Input, Output Waveform INPUT NOTE: AC Testing: All input signals (other than ...
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Burn-In Circuits GND RIO GND RIO V CL RIO GND RIO GND RIO V CL RIO GND RIO GND RIO GND RIO V CL RIO V CL RIO V CL OPEN OPEN OPEN OPEN GND GND GND ...
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Burn-In Circuits (Continued) RIO RIO RIO RIO RIO RIO RIO GND NOTES: = 5.5V ±0.5V, GND = 0V Input voltage limits (except clock): V (maximum (minimum) = 2.6V, V (clock -0.4V) minimum. ...
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Metallization Topology DIE DIMENSIONS: 249.2 x 290 METALLIZATION: Type: Silicon - Aluminum ±2k Å Å Thickness: 11k Metallization Mask Layout AD11 AD12 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK 80C86 GLASSIVATION: ...
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Instruction Set Summary MNEMONIC AND DESCRIPTION DATA TRANSFER MOV = MOVE: Register/Memory to/from Register Immediate to Register/Memory Immediate to Register Memory to Accumulator Accumulator to Memory Register/Memory to Segment Register †† Segment Register to Register/Memory PUSH = Push: Register/Memory Register ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Immediate to Register/Memory Immediate to Accumulator INC = Increment: Register/Memory Register AAA = ASCll Adjust for Add DAA = Decimal Adjust for Add SUB = Subtract: Register/Memory and Register to Either Immediate from ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION RCR = Rotate Through Carry Right AND = And: Reg./Memory and Register to Either Immediate to Register/Memory Immediate to Accumulator TEST = And Function to Flags, No Result: Register/Memory and Register Immediate Data ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Intersegment Intersegment Adding Immediate to SP JE/JZ = Jump on Equal/Zero JL/JNGE = Jump on Less/Not Greater or Equal JLE/JNG = Jump on Less or Equal/ Not Greater JB/JNAE = Jump on Below/Not ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION NOTES 8-bit accumulator AX = 16-bit accumulator CX = Count register DS= Data segment ES = Extra segment Above/below refers to unsigned value. Greater = more positive; Less = less positive ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -D- -A- E -B- bbb BASE Q PLANE -C- SEATING PLANE aaa ccc ...