CY29772AI Cypress Semiconductor Corporation., CY29772AI Datasheet

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CY29772AI

Manufacturer Part Number
CY29772AI
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07572 Rev. *A
Features
Block Diagram
• Output frequency range: 8.33 MHz to 200 MHz
• Input frequency range: 6.25 MHz to 125 MHz
• 2.5V or 3.3V operation
• Split 2.5V/3.3V outputs
• ±2% max. Output duty cycle variation
• 7 ps RMS typical Cycle-to-cycle jitter
• 6 ps RMS typical Period jitter
• 12 clock outputs: drive up to 24 clock lines
• One feedback output
• Three reference clock inputs: crystal or LVCMOS
• 300 ps max. output-output skew
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9772 and MPC972
• Industrial temperature range: –40°C to +85°C
• 52-pin 1.0-mm TQFP package
FB_SEL(0,1)
TCLK_SEL
SELA(0,1)
SELB(0,1)
SELC(0,1)
VCO_SEL
REF_SEL
FB_SEL2
INV_CLK
MR#/OE
PLL_EN
SDATA
TCLK0
TCLK1
XOUT
FB_IN
SCLK
XIN
Power-On
Reset
0
1
2
2
2
2
Detector
Phase
Output Disable
Data Generator
Circuitry
/4, /6, /8, /12
/4, /6, /8, /10
/4, /6, /8, /10
/2, /4, /6, /8
Sync Pulse
LPF
VCO
12
0
1
/2
0
1
D Q
D Q
D Q
D Q
D Q
D Q
198 Champion Court
Sync
Sync
Sync
Sync
Sync
Sync
Frz
Frz
Frz
Frz
Frz
Frz
2.5V or 3.3V, 200-MHz, 12-Output
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
QC2
QC3
FB_OUT
SYNC
Description
The CY29772 is a low-voltage high-performance 200-MHz
PLL-based zero delay buffer designed for high-speed
clock-distribution applications.
The CY29772 features one on-chip crystal oscillator and two
LVCMOS reference clock inputs and provides 12 outputs parti-
tioned in three banks of four outputs each. Each bank divides
the VCO output per SEL(A:C) settings, see Functional Table.
These dividers allow output to input ratios of 8:1, 6:1, 5:1, 4:1,
3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each
LVCMOS-compatible output can drive 50Ω series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces,
giving the device an effective fanout of 1:24.
The PLL is ensured stable given that the VCO is configured to
run between 200 MHz to 500 MHz. This allows a wide range
of output frequencies from 8 MHz to 200 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider, see Frequency Table.
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply.
Pin Configuration
TCLK_SEL
REF_SEL
FB_SEL2
MR#/OE
PLL_EN
San Jose
SDA TA
TCLK0
TCLK1
A V SS
A V DD
SCLK
XOUT
XIN
1
2
3
4
5
6
7
8
9
10
11
12
13
,
52 51 50 49 48 47 46 45 44 43 42 41 40
14 15 16 17 18 19 20 21 22 23 24 25 26
CA 95134-1709
C Y29772
Zero Delay Buffer
Revised September 1, 2005
39
38
37
36
35
34
33
32
31
30
29
28
27
CY29772
408-943-2600
V SS
QB0
V DDQB
QB1
V SS
QB2
V DDQB
QB3
FB_IN
V SS
FB_OUT
V DD
FB_SEL0
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CY29772AI Summary of contents

Page 1

Features • Output frequency range: 8.33 MHz to 200 MHz • Input frequency range: 6.25 MHz to 125 MHz • 2.5V or 3.3V operation • Split 2.5V/3.3V outputs • ±2% max. Output duty cycle variation • RMS typical ...

Page 2

Pin Description Pin Name I/O 11 XIN I 12 XOUT O 9 TCLK0 TCLK1 I, PU 44, 46, 48, 50 QA(3:0) O 32, 34, 36, 38 QB(3:0) O 16, 18, 21, 23 QC(3: FB_OUT ...

Page 3

Table 1. Frequency Table Feedback Output Divider VCO ÷4 Input Clock * 4 ÷6 Input Clock * 6 ÷8 Input Clock * 8 ÷10 Input Clock * 10 ÷12 Input Clock * 12 ÷16 Input Clock * 16 ÷20 Input ...

Page 4

Table 6. Function Table (FB_OUT) VCO_SEL FB_SEL2 FB_SEL1 FB_SEL0 ...

Page 5

Absolute Maximum Conditions Parameter Description V DC Supply Voltage Operating Voltage Input Voltage Output Voltage OUT V Output termination Voltage TT LU Latch-up Immunity R Power Supply Ripple PS T Temperature, ...

Page 6

AC Electrical Specifications (V DD Parameter Description f VCO Frequency VCO f Crystal Frequency Range XTAL f Input Frequency in f Input Duty Cycle refDC TCLK Input Rise/FallTime Maximum Output Frequency MAX f Serial ...

Page 7

AC Electrical Specifications (V DD Parameter Description t Cycle-to-Cycle Jitter JIT(CC) t Period Jitter JIT(PER) t I/O Phase Jitter JIT(φ) t Maximum PLL Lock Time LOCK AC Parameters (V = 3.3V ± 5 Parameter Description f VCO Frequency ...

Page 8

AC Parameters (V = 3.3V ± 5 Parameter Description tsk(B) Bank-to-Bank Skew t Output Disable Time PLZ Output Enable Time PZL PLL Closed-Loop Bandwidth (–3 dB) t Cycle-to-Cycle Jitter JIT(CC) t Period Jitter JIT(PER) ...

Page 9

VCO QA QC SYNC QA QC SYNC QC QA SYNC QA QC SYNC QC QA SYNC QA QC SYNC QA QC SYNC Power Management The individual output enable/freeze control of the CY29772 allows the user to implement unique power management ...

Page 10

Start Bit D0-D3 are the control bits for QA0-QA3, respectively D4-D7 are the control bits for QB0-QB3, respectively D8-D10 are the control bits for QC1-QC3, respectively D11 is the control bit for SYNC Table 7. Suggested Oscillator Crystal Parameters Parameter ...

Page 11

... Ordering Information Part Number CY29772AI 52-pin TQFP CY29772AIT 52-pin TQFP – Tape and Reel Lead-free CY29772AXI 52-pin TQFP CY29772AXIT 52-pin TQFP – Tape and Reel Package Drawing and Dimension 52-lead Thin Plastic Quad Flat Pack ( 1.0 mm) A52B Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders ...

Page 12

Document History Page Document Title:CY29772 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Document Number: 38-07572 REV. ECN No. Issue Date ** 129007 09/03/03 *A 395853 See ECN Document #: 38-07572 Rev. *A Orig. of Change Description of Change RGL ...

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