CY2PD817ZC Cypress Semiconductor Corporation., CY2PD817ZC Datasheet

no-image

CY2PD817ZC

Manufacturer Part Number
CY2PD817ZC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY2PD817ZC
Manufacturer:
CYPRESS
Quantity:
9
Cypress Semiconductor Corporation
Document #: 38-07574 Rev. **
Features
• DC to 320-MHz operation
• 50-ps output-output skew
• 30-ps cycle-cycle jitter
• 2.5V power supply
• LVPECL input @ 320-MHz Operation
• One LVPECL output @ 320-MHz Operation
• Four LVCMOS/LVTTL outputs @ 250 MHz/160 MHz
• Two LVCMOS/LVTTL outputs @ 250 MHz/80 MHz
• 45% to 55% output duty cycle
• Output divider control
• Output enable/disable control
• Operating temperature range: 0°C to +85°C
• 24-pin TSSOP
Block Diagram
PCLKI
PCLKI
CLRDIV
OE
÷ 4, ÷ 1
÷ 2, ÷ 1
320-MHz 1:7 PECL to PECL/CMOS Buffer
3901 North First Street
QA[0:1]
PCLKO
QB[0:3]
PCLKO
Description
The CY2PD817 is a low-voltage LVPECL-to-LVPECL and
LVCMOS fanout buffer designed for servers, data communi-
cations, and clock management.
The CY2PD817 is ideal for applications requiring mixed differ-
ential and single-ended clock distribution. This device accepts
an LVPECL input reference clock and provides one LVPECL
and six LVCMOS/LVTTL output clocks. The outputs are parti-
tioned into three banks of one, two, and four outputs. The
LVPECL output is a buffered copy of the input clock while the
LVCMOS outputs are divided by 1, 2, and 4. When CLRDIV is
set HIGH, the output dividers are set to 1. In this mode, the
maximum input frequency is limited to 250 MHz.
When OE is set HIGH, the outputs are disabled in a High-Z
state.
Pin Configuration
San Jose
CLRDIV
PCLKO
PCLKO
PCLKI
PCLKI
VDD
VDD
VSS
VSS
VSS
VDD
OE
,
1
2
3
4
5
6
7
8
9
10
11
12
CA 95134
24 TSSOP
Revised August 28, 2003
24
23
22
21
20
19
18
17
16
15
14
13
CY2PD817
VDD
QA0
QA1
VDD
QB0
QB1
VDD
QB2
QB3
VSS
VSS
VSS
408-943-2600

Related parts for CY2PD817ZC

CY2PD817ZC Summary of contents

Page 1

Features • 320-MHz operation • 50-ps output-output skew • 30-ps cycle-cycle jitter • 2.5V power supply • LVPECL input @ 320-MHz Operation • One LVPECL output @ 320-MHz Operation • Four LVCMOS/LVTTL outputs @ 250 MHz/160 MHz • ...

Page 2

Pin Description Pin Name 2 PCLKI 3 PCLKI 6 PCLKO 7 PCLKO 23, 22 QA[1,0] 14, 15, 18, 19 QB[3:0] 12 CLRDIV 10, 16, 20, 24 VDD 4, 8, 11, 13, 17, 21 VSS Table ...

Page 3

DC Electrical Specifications Parameter Description V Input Peak-Peak Voltage PP V Input Common Mode Range CMR V Input Voltage, Low IL V Input Voltage, High IH V Output Voltage, Low OL V Output Voltage, High OH V Output Voltage, Low ...

Page 4

ohm Differential Pulse Generator ohm ohm ohm T VTT Differential Output PECL_CLK V PECL_CLK PP Q tPD Differential Output ...

Page 5

... Ordering Information Part Number CY2PD817ZC CY2PD817ZCT Package Drawing and Dimensions 24-lead Thin Shrunk Small Outline Package (4.40-mm Body) Z24 All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07574 Rev. ** © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...

Page 6

Document History Page Document Title: CY2PD817 320-MHz 1:7 PECL to PECL/CMOS Buffer Document Number: 38-07574 REV. ECN NO. Issue Date ** 129024 08/29/03 Document #: 38-07574 Rev. ** Orig. of Change RGL New Data Sheet CY2PD817 Description of Change Page ...

Related keywords