CY2SSTV857ZC-27 Cypress Semiconductor Corporation., CY2SSTV857ZC-27 Datasheet

CY2SSTV857ZC-27

Manufacturer Part Number

CY2SSTV857ZC-27

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheet

1.CY2SSTV857ZC-27.pdf (9 pages)

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Cypress Semiconductor Corporation

Document #: 38-07464 Rev. *G

Features

• Operating frequency: 60 MHz to 200 MHz

• Supports 266, 333-MHz DDR SDRAM

• 10 differential outputs from 1 differential input

• Spread-Spectrum-compatible

• Low jitter (cycle-to-cycle): < 75

• Very low skew: < 100 ps

• Power management control input

• High-impedance outputs when input clock < 10 MHz

• 2.5V operation

• Pin-compatible with CDC857-2 and -3

• 48-pin TSSOP package

• Industrial temp. of –40° to +85°C

• Conforms to JEDEC DDR specification

Block Diagram

A V D D

F B IN #

C L K #

C LK

F B IN

P D #

3 7

1 6

3 6

3 5

1 3

1 4

P ow erdo w n

T e s t a n d

P L L

L o gic

•

3901 North First Street

1 0

2 0

1 9

2 2

2 3

4 6

4 7

4 4

4 3

3 9

4 0

2 9

3 0

2 7

2 6

3 2

3 3

Description

The CY2SSTV857-27 is a high-performance, low-skew,

low-jitter zero-delay buffer designed to distribute differential

clocks in high-speed applications. The CY2SSTV857-27

generates ten differential pair clock outputs from one differ-

ential pair clock input. In addition, the CY2SSTV857-27

features differential feedback clock outputs and inputs. This

allows the CY2SSTV857-27 to be used as a zero-delay buffer.

When used as a zero-delay buffer in nested clock trees, the

CY2SSTV857-27 locks onto the input reference and translates

with near-zero delay to low-skew outputs.

Differential Clock Buffer/Driver

Y 2

Y 3

Y 4

Y 5

Y 6

Y 7

Y 8

Y 9

Y 0

Y 0 #

Y 1

Y 1 #

Y 2 #

Y 3 #

Y 4 #

Y 5 #

Y 6 #

Y 7 #

Y 8 #

Y 9 #

F B O U T

F B O U T #

DDR333/PC2700-Compliant

Pin Configuration

•

V D D Q

A V D D

San Jose

A V S S

C L K #

V S S

C L K

Y 0 #

Y 1 #

Y 2 #

Y 3 #

Y 4 #

Y 0

Y 1

Y 2

Y 3

Y 4

CA 95134

1 0

1 1

1 2

1 3

1 4

1 5

1 6

1 7

1 8

1 9

2 0

2 1

2 2

2 3

2 4

Revised January 25, 2005

CY2SSTV857-27

•

4 8

4 7

4 6

4 5

4 4

4 3

4 2

4 1

4 0

3 9

3 8

3 7

3 6

3 5

3 4

3 3

3 2

3 1

3 0

2 9

2 8

2 7

2 6

2 5

408-943-2600

Y 5

Y 6

Y 7

P D #

V D D Q

Y 8

Y 9

V S S

Y 5 #

Y 6 #

V S S

Y 7 #

F B IN

V S S

Y 8 #

Y 9 #

V S S

V D D Q

F B IN #

F B O U T

V D D Q

F B O U T #

Related parts for CY2SSTV857ZC-27

CY2SSTV857ZC-27 Summary of contents

Page 1

Features • Operating frequency: 60 MHz to 200 MHz • Supports 266, 333-MHz DDR SDRAM • 10 differential outputs from 1 differential input • Spread-Spectrum-compatible • Low jitter (cycle-to-cycle): < 75 • Very low skew: < 100 ps • Power ...

Page 2

Pin Description Pin Number Pin Name 13, 14 CLK, CLK# 35 FBIN# 36 FBIN 3, 5, 10, 20, 22 Y(0: 19, 23 Y#(0:4) 27, 29, 39, 44, 46 Y(9:5) 26, 30, 40, 43, 47 Y#(9:5) 32 FBOUT ...

Page 3

Table 1. Function Table Inputs AVDD PD# CLK GND H L GND 2. 2. 2.5V H < 10 MHz CLKIN FBIN FBOUT CLKIN Yx or ...

Page 4

Yx DDR _SDRAM represents a capacitive load CLK CLK# Output load capacitance for 2 DDR-SDRAM Loads: 5 pF< CL< DDR-SDRAM represents a capacitive load CLK 120 Ohm CLK# 120 Ohm Output load capacitancce for 4 DDR-SDRAM Loads: 10 ...

Page 5

Figure 6. Differential Signal Using Direct Termination Resistor Document #: 38-07464 Rev ...

Page 6

Absolute Maximum Conditions Input Voltage Relative to V :...............................V SS Input Voltage Relative DDQ Storage Temperature: ................................ –65° 150°C Operating Temperature: .................................... 0°C to +85°C Maximum Power Supply: ................................................3.5V DC Electrical Specifications Parameter Description ...

Page 7

... Any Output to Any Output Skew SK(O) [14] t Phase Error PHASE Ordering Information Part Number CY2SSTV857ZC-27 48-pin TSSOP CY2SSTV857ZC-27T 48-pin TSSOP–Tape and Reel CY2SSTV857ZI-27 48-pin TSSOP CY2SSTV857ZI-27T 48-pin TSSOP–Tape and Reel Lead-free CY2SSTV857ZXC-27 48-pin TSSOP CY2SSTV857ZXC-27T 48-pin TSSOP–Tape and Reel ...

Page 8

Package Drawing and Dimension 0.500[0.019 12.395[0.488] 12.598[0.496] 0.500[0.020] 0.851[0.033] BSC 0.950[0.037] All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07464 Rev. *G © Cypress Semiconductor Corporation, 2005. The ...

Page 9

Document History Page Document Title: CY2SSTV857-27 Differential Clock Buffer/Driver, DDR333/PC2700-Compliant Document #: 38-07464 Rev. ECN No. Issue Date ** 117657 09/09/02 *A 118942 10/21/02 *B 121274 11/12/02 *C 122937 12/21/02 *D 127010 05/27/03 *E 129270 10/22/03 *F 202540 See ECN ...

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