CY7C1300A-100AC Cypress Semiconductor Corporation., CY7C1300A-100AC Datasheet

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CY7C1300A-100AC

Manufacturer Part Number
CY7C1300A-100AC
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-05075 Rev. *C
Features
Functional Description
The CY7C1300A SRAM integrates 131,072 × 36 SRAM cells
with advanced synchronous peripheral circuitry. It employs
high-speed, low-power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high-valued
resistors.
• Fast clock speed: 100 and 83 MHz
• Fast access times: 5.0/6.0 ns max.
• Single clock operation
• Single 3.3V –5% and +5% power supply V
• Separate V
• Two chip enables for simple depth expansion
• Address, data input, CE1X, CE2X, CE1Y, CE2Y, PTX,
• Concurrent Reads and Writes
• Two bidirectional data buses
• Can be configured as separate I/O
• Pass-through feature
• Asynchronous output enables (OEX, OEY)
• LVTTL-compatible I/O
• Self-timed Write
• Automatic power-down
• 176-pin TQFP package
PTY, WEX, WEY, and data output registers on-chip
Note:
1.
Logic Block Diagram
For 128K x 36 devices, AX and AY are 17-bit-wide buses.
CCQ
128K X 36 Dual I/O Dual Address Synchronous SRAM
for output buffer
[1]
3901 North First Street
CC
The CY7C1300A allows the user to concurrently perform
Reads, Writes, or pass-through cycles in combination on the
two data ports. The two address ports (AX, AY) determine the
Read or Write locations for their respective data ports (DQX,
DQY).
All input pins except output enable pins (OEX, OEY) are gated
by registers controlled by a positive-edge-triggered clock
(CLK) input. The synchronous inputs include all addresses,
data inputs, depth-expansion chip enables (CE1X, CE2X,
CE1Y and CE2Y), pass-through controls (PTX and PTY), and
Read–Write control (WEX and WEY).
The pass-through feature allows data to be passed from one
port to another, in either direction. The PTX input must be
asserted to pass data from port X to port Y. The PTY will
likewise pass data from port Y to port X. A pass-through
operation takes precedence over a Read operation.
When AX and AY are the same, certain protocols are followed.
If both ports are Read, the reads occur normally. If one port is
written and the other is read, the read from the array will occur
before the data is written. If both ports are written, only the data
on DQY will be written to the array.
The CY7C1300A operates from a +3.3V power supply. All
inputs and outputs are LVTTL-compatible. These dual I/O,
dual address synchronous SRAMs are well suited for ATM,
Ethernet switches, routers, cell/frame buffers, SNA switches,
and shared memory applications.
The CY7C1300A needs one extra cycle after power for proper
power-on reset. The extra cycle is needed after V
on the device.
This device is available in a 176-pin TQFP package.
San Jose
Y Y
CA 95134
Revised January 19, 2003
CY7C1300A
408-943-2600
CC
is stable

Related parts for CY7C1300A-100AC

CY7C1300A-100AC Summary of contents

Page 1

... SRAMs are well suited for ATM, Ethernet switches, routers, cell/frame buffers, SNA switches, and shared memory applications. The CY7C1300A needs one extra cycle after power for proper power-on reset. The extra cycle is needed after V on the device. This device is available in a 176-pin TQFP package. ...

Page 2

... DQY33 42 DQX33 43 VSS Document #: 38-05075 Rev. *C -100 5.0 500 100 176-pin TQFP CY7C1300A -83 Unit 6.0 ns 430 mA 100 mA VSS 132 DQX15 131 ...

Page 3

... This device contains circuitry that will ensure the outputs will be in High-Z during power-up Document #: 38-05075 Rev. *C Description [ CE2X CE1Y CE2Y CY7C1300A , V CC WEX WEY PTX Page ...

Page 4

... Max Device Deselected , 10.0 ns cycle, 100 MHz > V – 0.3V DDQ 12.0 ns cycle, 83 MHz Description Test Conditions T = 25° MHz 3.3V 3.3V CCQ CY7C1300A WEX WEY PTX Ambient [11] Temperature DDQ 0° ...

Page 5

... Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for t<200 ms. Document #: 38-05075 Rev. *C [17, 18 317 3.3V OUTPUT 351 INCLUDING JIG AND SCOPE (b) Test Conditions (@200lfm) Single-layer printed circuit board (@200lfm) Four-layer printed circuit board Bottom Top CY7C1300A [17] ALL INPUT PULSES 3.0V GND 1V/ns 1V/ns (c) TQFP Typ. Units 40 C/W 35 C/W 23 C/W 9 C/W ...

Page 6

... This parameter is sampled and not 100% tested. Document #: 38-05075 Rev. *C [17, 19, 20] Description [21] [21] [21] [21] is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1300A -100 -83 Min. Max. Min. Max 3.5 4.0 3.5 4.0 5.0 6.0 1 ...

Page 7

... CE LOW means (CE1X and CE1Y) equals LOW and (CE2X and CE2Y) equals HIGH. CE HIGH means (CE1X and CE1Y) equals HIGH or (CE2X and CE2Y) equals LOW. Document #: 38-05075 Rev Q(1) Q(2) Q( KQLZ t KQHZ Q(12) Q(13) Q(14) CY7C1300A [22 OEQ t OEHZ Q(5) Q(6) Q(7) t OELZ Q(16) Q(6) Q( Page ...

Page 8

... DQX CE# (See Note WEY# PORT Y OEY# DQY Document #: 38-05075 Rev. *C [22 D(2) D(3) D( D(14) D(15) D(5) PORT Y TAKES PRIORITY OVER PORT X WHEN AX=AY AND WRITING TO BOTH CY7C1300A [21 D(8) D( D(6) D(18) D(19) Page ...

Page 9

... CLK AX 1 WEX# PORT X OEX# PTY# PTX# DQX CE# (See Note WEY# PORT Y OEY# PTY# DQY Document #: 38-05075 Rev. *C [22] [21 D(2) D(3) D(X) D( Q(3) CY7C1300A D( KQHZ D(X) D(Y) Q(17) t KQX Page ...

Page 10

... Q(Value) = Value is the output of the data port. Document #: 38-05075 Rev. *C [22 TRY TO READ READ READ WRITE D(DEF) READ READ READ WRITE 2 1 D(XYZ) Q(PQR) CY7C1300A t KH READ READ READ 3 2 Q(PQR) Q(XYZ) Q(JKL) READ READ READ 3 2 D(JKL) Q(JKL) Page ...

Page 11

... Ordering Information Speed (MHz) Ordering Code 100 CY7C1300A-100AC 83 CY7C1300A-83AC Package Diagram 176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176 All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05075 Rev. *C © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...

Page 12

... Document Title: CY7C1300A 128K x 36 Dual I/O Dual Address Synchronous SRAM Document Number: 38-05075 Issue REV. ECN NO. Date ** 107304 06/08/01 *A 109296 10/31/01 *B 113017 04/09/02 *C 123844 01/19/03 Document #: 38-05075 Rev. *C Orig. of Change Description of Change NSL New Data Sheet CJM 1. Removed 133 MHz speed bin 2. Changed ESD voltage from >2001V to >1601V 3 ...

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