CY7C1300A-100AC Cypress Semiconductor Corporation., CY7C1300A-100AC Datasheet
CY7C1300A-100AC
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CY7C1300A-100AC Summary of contents
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... SRAMs are well suited for ATM, Ethernet switches, routers, cell/frame buffers, SNA switches, and shared memory applications. The CY7C1300A needs one extra cycle after power for proper power-on reset. The extra cycle is needed after V on the device. This device is available in a 176-pin TQFP package. ...
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... DQY33 42 DQX33 43 VSS Document #: 38-05075 Rev. *C -100 5.0 500 100 176-pin TQFP CY7C1300A -83 Unit 6.0 ns 430 mA 100 mA VSS 132 DQX15 131 ...
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... This device contains circuitry that will ensure the outputs will be in High-Z during power-up Document #: 38-05075 Rev. *C Description [ CE2X CE1Y CE2Y CY7C1300A , V CC WEX WEY PTX Page ...
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... Max Device Deselected , 10.0 ns cycle, 100 MHz > V – 0.3V DDQ 12.0 ns cycle, 83 MHz Description Test Conditions T = 25° MHz 3.3V 3.3V CCQ CY7C1300A WEX WEY PTX Ambient [11] Temperature DDQ 0° ...
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... Overshoot: VIH(AC) <VDD + 1.5V for t <tTCYC/2; undershoot: VIL(AC) < 0.5V for t <tTCYC/2; power-up: VIH < 2.6V and VDD <2.4V and VDDQ < 1.4V for t<200 ms. Document #: 38-05075 Rev. *C [17, 18 317 3.3V OUTPUT 351 INCLUDING JIG AND SCOPE (b) Test Conditions (@200lfm) Single-layer printed circuit board (@200lfm) Four-layer printed circuit board Bottom Top CY7C1300A [17] ALL INPUT PULSES 3.0V GND 1V/ns 1V/ns (c) TQFP Typ. Units 40 C/W 35 C/W 23 C/W 9 C/W ...
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... This parameter is sampled and not 100% tested. Document #: 38-05075 Rev. *C [17, 19, 20] Description [21] [21] [21] [21] is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ CY7C1300A -100 -83 Min. Max. Min. Max 3.5 4.0 3.5 4.0 5.0 6.0 1 ...
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... CE LOW means (CE1X and CE1Y) equals LOW and (CE2X and CE2Y) equals HIGH. CE HIGH means (CE1X and CE1Y) equals HIGH or (CE2X and CE2Y) equals LOW. Document #: 38-05075 Rev Q(1) Q(2) Q( KQLZ t KQHZ Q(12) Q(13) Q(14) CY7C1300A [22 OEQ t OEHZ Q(5) Q(6) Q(7) t OELZ Q(16) Q(6) Q( Page ...
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... DQX CE# (See Note WEY# PORT Y OEY# DQY Document #: 38-05075 Rev. *C [22 D(2) D(3) D( D(14) D(15) D(5) PORT Y TAKES PRIORITY OVER PORT X WHEN AX=AY AND WRITING TO BOTH CY7C1300A [21 D(8) D( D(6) D(18) D(19) Page ...
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... CLK AX 1 WEX# PORT X OEX# PTY# PTX# DQX CE# (See Note WEY# PORT Y OEY# PTY# DQY Document #: 38-05075 Rev. *C [22] [21 D(2) D(3) D(X) D( Q(3) CY7C1300A D( KQHZ D(X) D(Y) Q(17) t KQX Page ...
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... Q(Value) = Value is the output of the data port. Document #: 38-05075 Rev. *C [22 TRY TO READ READ READ WRITE D(DEF) READ READ READ WRITE 2 1 D(XYZ) Q(PQR) CY7C1300A t KH READ READ READ 3 2 Q(PQR) Q(XYZ) Q(JKL) READ READ READ 3 2 D(JKL) Q(JKL) Page ...
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... Ordering Information Speed (MHz) Ordering Code 100 CY7C1300A-100AC 83 CY7C1300A-83AC Package Diagram 176-lead Thin Quad Flat Pack (24 × 24 × 1.4 mm) A176 All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05075 Rev. *C © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...
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... Document Title: CY7C1300A 128K x 36 Dual I/O Dual Address Synchronous SRAM Document Number: 38-05075 Issue REV. ECN NO. Date ** 107304 06/08/01 *A 109296 10/31/01 *B 113017 04/09/02 *C 123844 01/19/03 Document #: 38-05075 Rev. *C Orig. of Change Description of Change NSL New Data Sheet CJM 1. Removed 133 MHz speed bin 2. Changed ESD voltage from >2001V to >1601V 3 ...