CY7C1304V25-167BZC Cypress Semiconductor Corporation., CY7C1304V25-167BZC Datasheet
CY7C1304V25-167BZC
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CY7C1304V25-167BZC Summary of contents
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... Advanced Information 9-Mb Pipelined SRAM with QDR™ Architecture Functional Description The CY7C1304V25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write op- erations ...
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... VDD VDDQ VDD VSS VDD VDDQ VSS VSS VDD VDDQ VSS VSS VSS VSS VSS VSS VSS VSS CY7C1304V25 RPS NC/ Gnd/ NC 18M 72M VSS VSS VDDQ VDDQ NC NC ...
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... When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. The CY7C1304V25 is organized internally as 128K x 72. Each read access consists of a burst of four sequential 18-bit transfers. Positive Output Clock Input used in conjunction with C to clock out the Read data from the device ...
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... The requested data FY/WRITE operations to a Byte Write operation. Single Clock Mode The CY7C1304V25 can be used with a single clock that con- trols both the input and output registers. In this mode the de- vice will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew be- tween the K/K and C/C clocks ...
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... Read/Write operations being initiated, with the first access be- ing a Read. Depth Expansion The CY7C1304V25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sam- pled on the rising edge of the Positive Input Clock only (K). ...
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... Application Example 18 Memory Controller 72 Q Din 72 Add. Cntr. CLK/CLK (input) CLK/CLK (output Advanced Information SRAM #1 SRAM # R= REF 6 CY7C1304V25 TERM REF Q R= ...
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... This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read request. Advanced Information RPS WPS DQ [6] [ D(A+00)at K(t+1) [ Q(A+00) at C(t+ High Previous State represents rising edge. 7 CY7C1304V25 D(A+01) at D(A+10) at D(A+11) at K(t+1) K(t+2) K(t+2) Q(A+01) at Q(A+10) at Q(A+11) at C(t+1) C(t+2) C(t+2) High-Z High-Z) High-Z Previous Previous Previous State State State ...
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... No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation. and BWS 0 8 CY7C1304V25 ) are written into the [17:0] ) are written into the [17: written into [8: written into ...
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... The TAP controller can- not be used to load address, data or control signals into the SRAM and cannot preload the Input or output buffers. The SRAM does not implement the 1149.1 commands EXTEST or 9 CY7C1304V25 ...
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... EXTEST EXTEST is a mandatory 1149.1 instruction which ex- ecuted whenever the instruction register is loaded with all 0s. EXTEST is not implemented in the CY7C1304V25 TAP con- troller, and therefore this device is not compliant to the 1149.1 standard. The TAP controller does recognize an all-0 instruction. When ...
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... Note: The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Advanced Information 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- CY7C1304V25 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT- EXIT1- PAUSE- EXIT2-IR 1 UPDATE- ...
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... Over the Operating Range Test Conditions I = 2.0mA 100 2.0mA 100 A OL GND DDQ /2, Undershoot V (AC)<0.5V for t<t /2, Power-up: VIH<2.6V and VDD<2.4V and VDDQ<1.4V for t<200ms. IL TCYC 12 CY7C1304V25 0 Selection Circuitry Min. Max. 1.7 2.1 0.7 0.2 1.7 V +0.3 DD –0.3 0 TDO Unit ...
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... CS CH 13. Test conditions are specified using the load in TAP AC test conditions. t Advanced Information [12, 13] Over the Operating Range Description / ns CY7C1304V25 Min. Max Unit 100 ns 10 MHz ...
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... TAP Timing and Test Conditions 1.25V 50 W TDO GND (a) Test Clock TCK Test Mode Select TMS Test Data-In TDI Test Data-Out TDO Advanced Information [13] 2. TMSS t TMSH t TDIS t TDIH t TDOX 14 CY7C1304V25 ALL INPUT PULSES 1.25V t TCYC t TDOV ...
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... Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. The SAMPLE Z command implemented by the CY7C1304V25 device will place the output buffers into a HIGH-Z condition. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO ...
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... Q12 54 D13 55 Q13 56 D14 57 Q14 58 D15 59 Q15 60 D16 61 Q16 62 D17 63 Q17 CY7C1304V25 Signal Name Bump (Don’t Care ...
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... MHz Max Both Ports De- 6.0 ns cycle, 167 MHz DD selected 7.5 ns cycle, 133 MHz 1/t In- IL MAX CYC, puts Static 10 ns cycle, 100 MHz 17 CY7C1304V25 Ambient [15] Temperature V DD 0°C to +70°C 2.5+/–100mV 1.4V to 1.9V Min. Max. 2.4 2.6 1.4 1.9 V /2+0.3 V DDQ DDQ V V /2-0 ...
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... At any given voltage and temperature t is less than t CHZ Advanced Information [17] Min. 6.0 2.4 2.4 2.7 0.0 [16] 1.2 0.7 , BWS ) 0 0.7 0.7 , BWS ) 0 0.7 [17, 18] [17, 18] 1.2 /I and load capacitance shown in ( test loads and t less than t . CLZ CHZ CO 18 CY7C1304V25 -167 -133 -100 Max Min. Max Min. Max 7.5 10.0 3.2 3.5 3.2 3.5 3.3 3.4 4.1 4.4 5.4 2.0 0.0 2.5 0.0 3.0 2.5 3.0 3.0 1.2 1.2 0.8 1.0 0.8 1.0 0.8 1.0 0.8 1.0 0.8 1.0 0.8 1 ...
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... W (a) 1304V25-2 Advanced Information Test Conditions MHz 2. 1.5V DDQ V /2 DDQ R=50 W REF DDQ OUTPUT Device 0.25V 5 pF Under ZQ Test RQ= 250 W INCLUDING (b) JIG AND SCOPE 19 CY7C1304V25 Max. Unit [16] ALL INPUT PULSES 1.25V 0.75V 1304V25-3 ...
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... (16: RPS Data Out Device originally deselected. Activity on the Write Port is unknown. = DON’T CARE Advanced Information CLZ Q(A+1) Q(A) Q(A+ KHCH t DOH DOH = UNDEFINED 20 CY7C1304V25 t CYC t KH Deselect Q(A+3) Q(B+1) Q(B+2) Q(B+3) Q(B) t CHZ t DOH ...
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... C and C reference to Data Outputs and do not affect Write operations. Activity on the Read Port is unknown. BWS LOW=Valid, Byte writes allowed, see Byte write table for details. x Advanced Information D(A+3) D(B) D(A) D(A+2) D(A+ DON’T CARE = UNDEFINED 21 CY7C1304V25 CYC t HC D(B+1) D(B+2) D(B+ ...
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... Switching Waveforms (continued) Read/Write/Deselect Sequence WPS RPS D [17:0] Q [17: Read Port previously deselected. BWS assumed active. x Advanced Information C D D(B+1) D(B+2) D(B+3) D(B) Q(A+1) Q(A+1) Q(A+3) Q(A) Q(A+2) Q(C) = UNDEFINED = DON’T CARE 22 CY7C1304V25 D(D) D(D+1) D(D+2) D(D+3) Q(G+1) Q(C+1) Q(C+2) Q(C+3) ...
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... Ordering Information Speed (MHz) Ordering Code 167 CY7C1304V25-167BZC/ 133 CY7C1304V25-133BZC/ 100 CY7C1304V25-100BZC/ Document #: 38–00925–** Package Diagram © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...