CY7C1334-100AC Cypress Semiconductor Corporation., CY7C1334-100AC Datasheet
CY7C1334-100AC
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CY7C1334-100AC Summary of contents
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... The CY7C1334 is a 3.3V, 64K by 32 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1334 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle ...
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... V 20 DDQ V 21 SSQ SSQ V 27 DDQ 100-Pin TQFP CY7C1334 2 CY7C1334 DDQ 76 V SSQ SSQ V 70 DDQ 69 DQ ...
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... Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. Ground for the I/O circuitry. Should be connected to ground of the system. No Connect. Reserved for drive strength control input. 3 CY7C1334 controls DQ , BWS controls 0 ...
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... Read/Modify/Write sequences, which can be reduced to sim- ple byte write operations. Because the CY7C1334 is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before present- ing data to the DQ output drivers ...
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... Burst Write Accesses The CY7C1334 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial ad- [ Cycle Description Truth Table ...
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... Latch-Up Current .................................................... >200 +150 C Operating Range +125 C 0.5V to +4.6V Range Com’l 0. 0.5V DDQ 0. 0.5V DDQ .Bytes written are determined by BWS . Bytes not selected during byte writes remain unaltered. All I/Os x [3:0] 6 CY7C1334 BWS BWS BWS ...
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... MHz 1/t MAX CYC 12.5-ns cycle, 80 MHz 20-ns cycle, 50 MHz Test Conditions MHz 3.3V 3.3V DD DDQ R=317 3.3V OUTPUT 5 pF R=351 GND INCLUDING JIG AND 1334-2 SCOPE (b) 7 CY7C1334 Min. Max. Unit 3.135 3.465 V 3.135 3.465 V 2.4 V 0.4 V 2 0.3 0 ...
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... Min. Max. Min. 7.5 10 2.2 3.5 2.2 3.5 4.2 1.5 1.5 2.0 2.2 0.5 0.5 2.0 2.2 0.5 0.5 2.0 2.2 0.5 0.5 2.0 2.2 0.5 0.5 1.7 2.0 0.5 0.5 2.0 2.2 0.5 0.5 1.5 3.5 1.5 1.5 1.5 [13, 15, 16, 17] 4.2 [13, 15, 16, 17] 1.0 1.0 4.2 is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ 8 CY7C1334 TQFP Typ. Units Notes 28 C C/W JC -100 -80 -50 Max. Min. Max. Min. Max. 12.5 20.0 4.0 6.0 4.0 6.0 5.0 7.0 10.0 1.5 1.5 2.5 3.0 1.0 1.5 2.5 3.0 1.0 1.5 2.5 3.0 1.0 1.5 2.5 3.0 1.0 1.5 2.5 3.0 1.0 1.5 2.5 3.0 1.0 1.5 3.5 1.5 3 ...
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... In Out Out defines a write cycle (see Write Cycle Description table). [3: and CE . All chip enables need to be active in order to select DON’T CARE = UNDEFINED 9 CY7C1334 t t CENH CENS RA7 CEN HIGH blocks all synchronous inputs t CHZ Out Out ...
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... AH AS WA2 CHZ Q1+2 Q1+3 D2 Q1+1 Out Out In Out define a write cycle (see Write Cycle Description table). [3: and CE . All chip enables need to be active in order to select DON’T CARE = UNDEFINED 10 CY7C1334 RA3 t CLZ D2+2 D2+3 D2+1 Out input signals. [3:0] ...
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... OE Timing Ordering Information Speed (MHz) Ordering Code 133 CY7C1334-133AC 100 CY7C1334-100AC 80 CY7C1334-80AC 50 CY7C1334-50AC Document #: 38-00638-B Package Diagram 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product ...