CY2DP314OXIT Cypress Semiconductor Corporation., CY2DP314OXIT Datasheet

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CY2DP314OXIT

Manufacturer Part Number
CY2DP314OXIT
Description
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY2DP314OXIT

Dc
0619
Cypress Semiconductor Corporation
Document #: 38-07550 Rev.*E
Features
• Four ECL/PECL differential outputs
• One ECL/PECL differential or single-ended inputs
• One HSTL differential or single-ended inputs (CLKB)
• Hot-swappable/-insertable
• 50-ps output-to-output skew
• 150-ps device-to-device skew
• 400-ps propagation delay (typical)
• 0.8-ps RMS period jitter (max.)
• 1.5-GHz operation (2.7-GHz maximum toggle
• PECL and HSTL mode supply range: V
• ECL mode supply range: V
• Industrial temperature range: –40°C to 85°C
• 20-pin SSOP package
• Temperature compensation like 100K ECL
Block Diagram
(CLKA)
frequency)
3.3V±5% with V
with V
CLK_SEL
CLKA#
CLKB#
CLKA
CLKB
VCC
CC
VCC
= 0V
VEE
VEE
VEE
EE
= 0V
E E
= –2.5V± 5% to –3.3V±5%
1 of 2:4 Differential Clock/Data Fanout Buffer
CC
= 2.5V± 5% to
3901 North First Street
Q0
Q0#
Q1
Q1#
Q2
Q2#
Q3
Q3#
Functional Description
The CY2DP314 is a low-skew, low propagation delay 2-to-4
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz (full
swing).
The device features two differential input paths that are multi-
plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP314 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on HSTL
or LVCMOS /LVTTL single-ended signal to four ECL/PECL
differential loads.
Since the CY2DP314 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP314 delivers consistent performance
over various platforms.
CLK_SEL
Pin Configuration
San Jose
CLKA#
CLKB#
CLKA
CLKB
VCC
VCC
VCC
VEE
NC
,
20 pin SSOP
1
2
3
4
5
6
7
8
9
10
CA 95134
Revised September 27, 2004
20
19
18
17
16
15
14
13
12
11
VCC
Q0
Q0#
Q1
Q1#
Q2
Q2#
VCC
CY2DP314
Q3
Q3#
408-943-2600

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CY2DP314OXIT Summary of contents

Page 1

Differential Clock/Data Fanout Buffer Features • Four ECL/PECL differential outputs • One ECL/PECL differential or single-ended inputs (CLKA) • One HSTL differential or single-ended inputs (CLKB) • Hot-swappable/-insertable • 50-ps output-to-output skew • 150-ps device-to-device skew • ...

Page 2

Pin Definitions Pin Name 1,10,11,20,3 VCC CLK_SEL 5 CLKA 6 CLKA# 7 CLKB 8 CLKB# [2] 9 VEE 18,16,14,12 Q[0:3]# 19,17,15,13 Q[0:3] Table 1. Control CLK_SEL 0 CLKA, CLKA# input pair is active (Default condition with no ...

Page 3

Absolute Maximum Ratings Parameter Description V Positive Supply Voltage CC V Negative Supply Voltage EE T Temperature, Storage S T Temperature, Junction J ESD ESD Protection h M Moisture Sensitivity Level SL Gate Count Total Number of Used Gates Multiple ...

Page 4

ECL DC Electrical Specifications Parameter Description V Negative Power Supply EE V ECL Input Differential cross point CMR [7] voltage V Output High Voltage OH V Output Low Voltage –3.3V ± –2.5V ± ...

Page 5

Timing Definitions > ...

Page 6

Test Configuration Standard test load using a differential pulse generator and differential measurement instrument ...

Page 7

... Figure 9. Termination for LVPECL to HTSL interface for VCC=2.5V would use X=50 Ohms, Y=2300 Ohms, and Z=1000 Ohms. See application note entitled PECL Translation, SAW Oscillators, and Specs Ordering Information Part Number CY2DP314OI CY2DP314OIT Lead-free CY2DP314OXI CY2DP314OXIT Document #: 38-07550 Rev.* " " ...

Page 8

... Package Drawing and Dimensions 20-Lead (5.3 mm) Shrunk Small Outline Package O20 FastEdge is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07550 Rev.*E © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product ...

Page 9

Document History Page Document Title: CY2DP314 FastEdge¥ SERIES 1 of 2:4 Differential Clock/Data Fanout Buffer Document Number: 38-07550 Orig. of REV. ECN NO. Issue Date Change ** 126779 06/13/03 RGL *A 128940 08/19/03 RGL *B 207710 See ECN RGL *C ...

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