UPD70P3000GC-25-7EA Renesas Electronics Corporation., UPD70P3000GC-25-7EA Datasheet
UPD70P3000GC-25-7EA
Related parts for UPD70P3000GC-25-7EA
UPD70P3000GC-25-7EA Summary of contents
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SINGLE-CHIP MICROCONTROLLER The PD70P3000 is a one-time PROM version of the PD703000. A program can be written only once to the PROM of the one-time PROM and this model is useful for small-scale production of a variety of application ...
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PIN CONFIGURATION (Top View) (1) Normal operation mode P64/A20 1 P63/A19 2 P62/A18 3 P61/A17 4 P60/A16 P57/AD15 8 P56/AD14 9 P55/AD13 10 P54/AD12 11 P53/AD11 12 P52/AD10 13 P51/AD9 14 P50/AD8 15 ...
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P00-P07 : Port0 P10-P17 : Port1 P20-P27 : Port2 P30-P37 : Port3 P40-P47 : Port4 P50-P57 : Port5 P60-P67 : Port6 P90-P97 : Port9 P100-P103 : Port10 TO10, TO11 : Timer Output TCLR1 : Timer Clear TI1 : Timer Input ...
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PROM programming mode A16 8 A15 9 A14 10 A13 11 A12 12 A11 13 A10 ...
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INTERNAL BLOCK DIAGRAM NMI INTP00-INTP03 INTC INTP10-INTP13 RPU TO10, TO11 TCLR1 TI1 SIO TXD UART RXD BRG SO SI CSI SCK Note In PROM programming mode PROM CPU 32-bit bytes barrel shifter Multiplier System ...
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DIFFERENCES BETWEEN PD70P3000 and PD703000 ····························································· PIN FUNCTIONS ································································································································ 8 2.1 Normal Operation Mode (MODE0 = L, MODE1 = H) ················································································ 2.1.1 Port pins ········································································································································· 2.1.2 Pins other than port pins ·············································································································· 2.2 PROM Programming Mode (MODE0 ...
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DIFFERENCES BETWEEN PD70P3000 and PD703000 The PD70P3000 is a PROM version of the PD703000. Therefore, these two models are identical except for differences because of the ROM specifications (for example, specifications concerning writing and verifying). Table 1-1 shows the ...
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PIN FUNCTIONS 2.1 Normal Operation Mode (MODE0 = L, MODE1 = H) 2.1.1 Port pins Pin Name I/O P00 I/O Port 0 P01 8-bit I/O port. P02 Can be set in input or output mode in 1-bit units. P03 ...
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Pin Name I/O P90 I/O Port 9 P91 8-bit I/O port. P92 Can be set in input or output mode in 1-bit units. P93 P94 P95 P96 P97 P100 I/O Port 10 P101 4-bit I/O port. P102 Can be set ...
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Pin Name I/O R/W Output External read/write status output DSTB External data strobe signal output ASTB External address strobe signal output ST0 External bus cycle status output ST1 HLDAK Output Bus hold acknowledge output HLDRQ Input Bus hold request input ...
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PROM Programming Mode (MODE0 = H, MODE1 = H) Pin Name P60-P67 Low-order address (A0 through A7) input P50, P20, P51-P57 High-order address (A8 through A16) input P40-P47 Data I/O P25 CE (chip enable) input P26 OE (output enable) ...
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I/O Circuits of Pins and Recommended Connections of Unused Pins Table 2-1 shows the I/O circuit type of each pin in the normal operation mode, and the recommended connections of the unused pins. Figure 2-1 shows a partially simplified ...
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Figure 2-1. I/O Circuits of Pins Type P-ch IN N-ch Type 2 IN Schmitt trigger input with hysteresis characteristics Type P-ch OUT N-ch PD70P3000 Type Data P-ch Output N-ch disable Input ...
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PROM PROGRAMMING The PD70P3000 has a 32K 8 bit PROM that can be electrically written. To program this PROM, set the PROM programming mode by using the V The programming characteristics are compatible with those of the PD27C1001A. Table ...
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Page data latch mode The page data latch mode can be set by making the CE and PGM pins high and OE pin low at the beginning of the page write mode. In the page data latch mode, 1 ...
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PROM Writing Procedure Figure 3-1. Flowchart in Page Program Mode Address=Address+1 16 Start MODE1=MODE0=H Supply initial address V =6 =12 X=0 Latch Address=Address+1 Latch Address=Address+1 Latch ...
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Figure 3-2. PROM Writing/Verify Timing (page program mode) Page data latch A2-A16 (input) Address input A0, A1 (input) Data input D0-D7 (I/O) +12 +6 (input) PGM (input) OE (input) ...
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Figure 3-3. Flowchart in Byte Program Mode Address=Address+1 18 Start MODE1=MODE0=H Supply initial address V =6 =12 X=0 X=X+1 Supply write data Supply program pulse FAIL Verify ...
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Figure 3-4. PROM Writing/Verifying Timing (byte program mode) Byte program A0-A16 (input) D0-D7 (I/O) Data input +12 +6 (input) PGM (input) OE (input) Remark The broken line indicates the ...
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PROM Reading Procedure The procedure to read the contents of the PROM to the external data bus (D0 through D7 follows: (1) Fix the MODE0 and MODE1 pins to low level. Connect the unused pins by referring ...
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SCREENING OF ONE-TIME PROM DEVICE Because of its structure, the one-time PROM cannot be completely tested by NEC before shipment recommended to perform screening to verify the PROM, after writing the necessary data to the PROM and ...
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ELECTRICAL SPECIFICATIONS 6.1 Normal Operation Mode Corresponding Electrical Specifications Part Number PD70P3000GC-25-7EA PD70P3000GC-33-7EA 6.1.1 When Absolute Maximum Ratings ( Parameter Symbol Supply voltage ...
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Capacitance ( Parameter Symbol Input capacitance C I I/O capacitance C IO Output capacitance C O Operating Conditions Operation Mode Internal Operating Clock Frequency ( ) Direct mode ...
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Recommended Oscillation Circuit (a) Ceramic resonator connection (TDK, Murata Mfg.: T Oscillation Manufacturer Part Number Frequency f (MHz) XX TDK Corp. FCR2.0MC3 2.0 CCR3.2MC3 3.2 FCR5.0MC5 5.0 CCR5.0MC3 5.0 CCR6.6MC3 6.6 Kyocera KBR-2.0MS 2.0 Corp. KBR-2.7MS 2.7 KBR-3.2MS 3.2 KBR-5.0MSA ...
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External clock input Caution Input CMOS level voltage to the X1 pin Open External clock PD70P3000 25 ...
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DC Characteristics (T = – – Parameter Symbol Input voltage, high V Input voltage, low V X1 clock input voltage, high V X1 clock input voltage, low V ...
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Data Retention Characteristics (T = –40 to +85 C –20 to +70 C): A Parameter Symbol Data hold voltage V Data hold current I DDDR Supply voltage rise time t RVD Supply voltage fall time t FVD ...
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AC Characteristics (T = – – test input wave (a) RESET, P02/TCLR1, P03/TI1, P04/INTP10 through P07/INTP13, P20/NMI, P21/INTP00 through P24/ INTP03, P26, P27, P31/SI, P32/SCK, P36, P37, ...
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Clock timing Parameter Symbol X1 input cycle <1> X1 input width, high <2> X1 input width, low <3> X1 input rise time <4> X1 input fall time <5> CPU operating frequency — CLKOUT output cycle <6> CLKOUT width, high ...
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Input waveform (a) RESET, P02/TCLR1, P03/TI1, P04/INTP10 through P07/INTP13, P20/NMI, P21/INTP00 through P24/ INTP03, P26, P27, P31/SI, P32/SCK, P36, P37, MODE0, MODE1, CKSEL, X1 Parameter Symbol Input rise time <12> Input fall time <13> 0 ...
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Output waveform (other than CLKOUT) Parameter Symbol Output rise time <16> Output fall time <17> 2.2 V Output signal 0.8 V (4) Reset timing Parameter Symbol RESET width, high <18> RESET width, low <19> Remark T : oscillation stabilization ...
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Read timing (1/2) Parameter Symbol CLKOUT address delay time <20> CLKOUT address float delay time <21> CLKOUT ASTB delay time <22> CLKOUT DSTB delay time <23> CLKOUT status delay time <24> Data input setup time (vs. CLKOUT ) <25> ...
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Read Timing (2/2): 1 wait T1 CLKOUT (output) < 20 > A16-A23 (output), Note AD0-AD15 (I/O) A0-A15 (output) < 22 > < 30 > ASTB (output) < 43 > DSTB (output) < 24 > < 40 > ST0, ST1 ...
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Write timing (1/2) Parameter Symbol CLKOUT address delay time <20> CLKOUT ASTB delay time <22> CLKOUT DSTB delay time <23> CLKOUT status delay time <24> WAIT setup time (vs. CLKOUT ) <27> WAIT hold time (vs. CLKOUT ) <28> ...
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Write timing (2/2): 1 wait T1 CLKOUT (output) < 20 > A16-A23 (output), Note AD0-AD15 (I/O) A0-A15 (output) < 22 > < 30 > ASTB (output) < 43 > DSTB (output) < 24 > < 40 > ST0, ST1 ...
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Bus hold timing (1/2) Parameter Symbol HLDRQ setup time (vs. CLKOUT ) <57> HLDRQ hold time (vs. CLKOUT ) <58> CLKOUT HLDAK delay time <59> HLDRQ width, high <60> HLDAK width, low <61> CLKOUT bus float delay time <62> ...
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Bus hold timing (2/2) CLKOUT (output) <57> <58> <57> HLDRQ (input) <64> HLDAK (output) Note A16-A23 (output) D0-D15 AD0-AD15 (I/O) (input or output) ASTB (output) DSTB (output) ST0, ST1 (output) R/W (output) Note UBEN (output) and LBEN (output) Remark ...
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Interrupt timing Parameter Symbol NMI width, high <66> NMI width, low <67> INTPn width, high <68> INTPn width, low <69> Remark CYK NMI (input) INTPn (input) Remark n = 00, 01, 02, 03, 10, 11, 12, ...
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CSI timing (a) Master mode Parameter Symbol SCK cycle <70> SCK width, high <71> SCK width, low <72> SI setup time (vs. SCK ) <73> SI hold time (vs. SCK ) <74> SO output delay time (vs. SCK ) ...
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RPU timing Parameter Symbol TI1 width, high <77> TI1 width, low <78> TCLR1 width, high <79> TCLR1 width, low <80> Remark CYK TI1 (input) TCLR1 (input) 40 Condition PD70P3000-25 MIN. MAX ...
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When V = 3 Absolute Maximum Ratings ( Parameter Symbol Supply voltage Input voltage Clock input voltage V X Output current, ...
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Recommended Oscillation Circuit (a) Ceramic resonator connection (T Oscillation Manufacturer Part Number Frequency f (MHz) XX TDK Corp FCR2.0MC3 2.0 CCR3.2MC3 3.2 Murata Mfg. CSA2.00MG 2.0 Co., Ltd. CST2.00MG 2.0 CSA2.70MG 2.7 CST2.70MGW 2.7 CSA3.20MG 3.2 CST3.20MGW 3.2 Cautions 1. ...
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DC Characteristics (T = – Parameter Symbol Input voltage, high V Input voltage, low V X1 clock input voltage, high V X1 clock input voltage, low V Schmitt trigger input threshold voltage V V Schmitt ...
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Data Retention Characteristics (T = – Parameter Symbol Data hold voltage V Data hold current I DDDR Supply voltage rise time t RVD Supply voltage fall time t FVD Supply voltage hold time t HVD (vs. ...
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AC Characteristics (T = – test input wave (a) RESET, P02/TCLR1, P03/TI1, P04/INTP10 through P07/INTP13, P20/NMI, P21/INTP00 through P24/ INTP03, P26, P27, P31/SI, P32/SCK, P36, P37, MODE0, MODE1, CKSEL ...
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Clock timing Parameter Symbol X1 input cycle <1> X1 input width, high <2> X1 input width, low <3> X1 input rise time <4> X1 input fall time <5> CPU operating frequency — CLKOUT output cycle <6> CLKOUT width, high ...
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Input waveform (a) RESET, P02/TCLR1, P03/TI1, P04/INTP10 through P07/INTP13, P20/NMI, P21/INTP00 through P24/ INTP03, P26, P27, P31/SI, P32/SCK, P36, P37, MODE0, MODE1, CKSEL, X1 Parameter Symbol Input rise time <12> Input fall time <13> 0 ...
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Output waveform (other than CLKOUT) Parameter Symbol Output rise time <16> Output fall time <17> 2.2 V Output signal 0.8 V (4) Reset timing Parameter Symbol RESET width, high <18> RESET width, low <19> Remark T : oscillation stabilization ...
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PD70P3000 49 ...
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Read timing (1/2) Parameter Symbol CLKOUT address delay time <20> CLKOUT address float delay time <21> CLKOUT ASTB delay time <22> CLKOUT DSTB delay time <23> CLKOUT status delay time <24> Data input setup time (vs. CLKOUT ) <25> ...
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Read Timing (2/2): 1 wait T1 CLKOUT (output) < 20 > A16-A23 (output), Note AD0-AD15 (I/O) A0-A15 (output) < 22 > < 30 > ASTB (output) < 43 > DSTB (output) < 24 > < 40 > ST0, ST1 ...
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Write timing (1/2) Parameter Symbol CLKOUT address delay time <20> CLKOUT ASTB delay time <22> CLKOUT DSTB delay time <23> CLKOUT status delay time <24> WAIT setup time (vs. CLKOUT ) <27> WAIT hold time (vs. CLKOUT ) <28> ...
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Write timing (2/2): 1 wait T1 CLKOUT (output) < 20 > A16-A23 (output) Note AD0-AD15 (I/O) A0-A15 (output) < 22 > < 30 > ASTB (output) < 43 > DSTB (output) < 24 > < 40 > ST0, ST1 ...
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Bus hold timing (1/2) Parameter Symbol HLDRQ setup time (vs. CLKOUT ) <57> HLDRQ hold time (vs. CLKOUT ) <58> CLKOUT HLDAK delay time <59> HLDRQ width, high <60> HLDAK width, low <61> CLKOUT bus float delay time <62> ...
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Bus hold timing (2/2) CLKOUT (output) <57> <58> HLDRQ (input) HLDAK (output) Note A16-A23 (output) D0-D15 AD0-AD15 (I/O) (input or output) ASTB (output) DSTB (output) ST0, ST1 (output) R/W (output) Note UBEN (output) and LBEN (output) Remark The broken ...
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Interrupt timing Parameter Symbol NMI width, high <66> NMI width, low <67> INTPn width, high <68> INTPn width, low <69> Remark CYK NMI (input) INTPn (input) Remark n = 00, 01, 02, 03, 10, 11, 12, ...
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CSI timing (a) Master mode Parameter Symbol SCK cycle <70> SCK width, high <71> SCK width, low <72> SI setup time (vs. SCK ) <73> SI hold time (vs. SCK ) <74> SO output delay time (vs. SCK ) ...
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RPU timing Parameter Symbol TI1 width, high <77> TI1 width, low <78> TCLR1 width, high <79> TCLR1 width, low <80> Remark CYK TI1 (input) TCLR1 (input) 58 Condition t WTIH t WTIL t WTCH t WTCL ...
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PROM Programming Mode DC Programming Characteristics PROM write mode ( Parameter Symbol Input voltage, high V IH Input voltage, low V IL Output voltage, high V OH Output voltage, low V OL ...
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AC Programming Characteristics (1) PROM write mode timing (page program mode 6.5 0. Parameter Symbol Address setup time (vs <101> setup time <102> ...
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PROM write mode timing (page program mode) (2/2) Page data latch A2-A16 (input) < 101 > < 106 > A0, A1 (input) < 104 > < 108 > D0-D7 (I/O) Note 1 Note 1 < 110 > ...
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PROM write mode timing (byte program mode 6.5 0. Parameter Symbol Address setup time (vs. PGM ) <101> setup time <102> setup time (vs. ...
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PROM read mode timing ( Parameter Symbol Address data output delay time <118> data output delay time <119> data output delay time <120> data output float delay time <109> t ...
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PROM programming mode setting timing (T Parameter PROM programming mode setup time RESET (input A0-A16 (input) Invalid Symbol Condition ...
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CHARACTERISTICS CURVES (reference) I vs. (V – 25° 5 –3.0 –2.0 –1 0.2 0.4 Supply voltage - high-level output voltage ...
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PACKAGE DRAWINGS 100 PIN PLASTIC QFP (FINE PITCH 100 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition ...
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RECOMMENDED SOLDERING CONDITIONS Solder this product under the folllowing recommended conditions. For the details of the recommended soldering conditions, refer to Information Document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and soldering conditions other than those recommended, ...
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APPENDIX PROM WRITING TOOLS (1) Hardware tools Product Product Name PROM programmer PG-1500 UNISITE 2900 3900 MODEL1890A AF-9705 Rev.01.37 or higher Algorithm Rev.02.40 or higher PROM programmer PA-70P3000GC adapter (2) Software tools Product Host Machine PG-1500 controller PC-9800 series MS-DOS ...
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PD70P3000 69 ...
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NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
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Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
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Related documents : PD703000, 703001 Data Sheet (U10987E) V850 Family Instruction Table (U10229E) V851 Register Table (U10662J) (Japanese version) Some of the related documents are preliminary editions but are not so specified here. V850 Family, V851, and QTOP are trademarks ...