LH5496D-35 Sharp, LH5496D-35 Datasheet
LH5496D-35
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LH5496D-35 Summary of contents
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LH5496/96H FEATURES Fast Access Times: 15 */20/25/35/50/65/80 ns Full CMOS Dual Port Memory Array Fully Asynchronous Read and Write Expandable-in Width and Depth Full, Half-Full, and Empty Status Flags Read Retransmit Capability TTL Compatible I/O Packages: 28-Pin, 300-mil PDIP 28-Pin, ...
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LH5496/96H RESET RS LOGIC INPUT W PORT CONTROL PIN DESCRIPTIONS PIN PIN TYPE * DESCRIPTION D – D Input Data Bus – Q Output Data Bus O Write Request I R Read Request ...
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CMOS 512 9 FIFO ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage to V Potential SS Signal Pin Voltage to V Potential Output Current Storage Temperature Range Power Dissipation (Package Limit) DC Voltage Applied To Outputs In High-Z State ...
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LH5496/96H AC TEST CONDITIONS PARAMETER Input Pulse Levels Input Rise and Fall Times (10% to 90%) Input Timing Reference Levels Output Reference Levels Output Load, Timing Tests 1,2 CAPACITANCE PARAMETER C (Input Capacitance (Output Capacitance) OUT NOTES: 1. ...
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CMOS 512 9 FIFO AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER t Read Cycle Time RC t Access Time A t Read Recover Time Read Pulse Width RPW t Data Bus Active from Read LOW RLZ Data Bus Active ...
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LH5496/96H OPERATIONAL DESCRIPTION Reset The device is reset whenever the Reset pin (RS) is taken to a LOW state. The reset operation initializes both the read and write address pointers to the first memory location. The XI and FL pins ...
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CMOS 512 9 FIFO TIMING DIAGRAMS RS R,W EF FF,HF NOTES RSC RS RSR 2. W and R V around the rising edge of RS The Data Out pins (D - ...
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LH5496/96H TIMING DIAGRAMS (cont’d) LAST WRITE Figure 7. Full Flag from Last Write to First Read LAST READ NOTE: The Data Out pins ( are forced into high-impedance ...
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CMOS 512 9 FIFO TIMING DIAGRAMS (cont’ NOTES RPE RPW Effective Read Pulse Width after Empty Flag HIGH. RPE 3. ...
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LH5496/96H TIMING DIAGRAMS (cont’ NOTES RPE RPW Effective Read Pulse Width after Empty Flag HIGH. RPE 3. The Data Out pins ( are forced into a 0 ...
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CMOS 512 9 FIFO TIMING DIAGRAMS (cont’d) RT R,W NOTES RTC RT RTR 2. EF, HF and FF may change state during retransmit, but flags will be valid at t WRITE TO LAST AVAILABLE ...
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LH5496/96H OPERATIONAL MODES Single Device Configuration When depth expansion is not required for the given application, the device is placed in Single mode by tying the Expansion In pin (XI) to ground. This pin is internally sampled during reset. WRITE ...
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CMOS 512 9 FIFO OPERATIONAL MODES (cont’d) Depth Expansion Depth expansion is implemented by configuring the required number of FIFOs in Expansion mode. In this arrangement, the FIFOs are connected in a circular fash- ion with the Expansion Out pin ...
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LH5496/96H OPERATIONAL MODES (cont’d) Compound Expansion A combination of width and depth expansion can be easily implemented by operating groups of depth expanded FIFOs in parallel. Bidirectional Operation Applications which require bidirectional data buffering between two systems can be realized ...
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CMOS 512 9 FIFO PACKAGE DIAGRAMS 28SK-DIP (DIP028-P-0300 35.00 [1.378] 34.40 [1.354] 2.54 [0.100] 0.56 [0.022] TYP. 0.36 [0.014] MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT 28DIP (DIP028-P-0600 36.30 [1.429] 35.70 [1.406] 2.54 [0.100] 0.60 ...
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LH5496/96H 32PLCC (PLCC32-P-R450) 15.11 [0.595] 14.86 [0.585] 14.05 [0.553] 13.89 [0.547] 3.56 [0.140] 3.12 [0.123] 0.10 [0.004] MAXIMUM LIMIT DIMENSIONS IN MM (INCHES) MINIMUM LIMIT ORDERING INFORMATION LH5496/96H X Device Type Temperature Package Range * LH5496 only Example: LH5496U-25 (CMOS ...