HD6432246FA Renesas Electronics Corporation., HD6432246FA Datasheet
HD6432246FA
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HD6432246FA Summary of contents
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REJ09B0355-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 Rev.3.00 Revision date: Mar. 26, ...
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This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...
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Rev.3.00 Mar. 26, 2007 Page iv of xlii REJ09B0355-0300 ...
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The H8S/2245 Group is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip peripheral functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with ...
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Rev.3.00 Mar. 26, 2007 Page vi of xlii REJ09B0355-0300 ...
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Main Revisions for This Edition Item Page Revision (See Manual for Details) All — 1.1 Overview 2 Table 1.1 Overview 1.3.2 Pin Functions Each Operating Mode 11 Table 1.2 Pin Functions 11 in Each Operating Mode 1.3.3 ...
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Item Page Revision (See Manual for Details) 2.3 Address Space 27 2.6.1 Overview 36 Table 2.1 Instruction Classification 37 Table 2.3 Data Transfer 40 Instructions Table 2.4 Arithmetic 41, Operation Instructions 42 42 Table 2.10 Block Data 48 Transfer Instructions ...
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Item Page Revision (See Manual for Details) 3.4 Pin Functions in 77 Each Operating Mode Table 3.3 Pin Functions in Each Operating Mode 5.1.2 Block Diagram 104 Figure 5.1 Block Diagram 5.3.1 External Interrupts 112 Figure 5.3 Timing of Setting ...
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Item Page Revision (See Manual for Details) 6.5.5 Wait Control 165 Figure 6.18 Example of Wait State Insertion Timing 7.2.5 DTC Transfer 184 Count Register A (CRA) Rev.3.00 Mar. 26, 2007 Page x of xlii REJ09B0355-0300 Figure 6.18 amended By ...
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Item Page Revision (See Manual for Details) 7.2.8 DTC Vector 186 Register (DTVECR) 7.3.2 Activation 190 Sources 7.3.8 Chain Transfer 199 Bit figure amended Bit : SWDTE DTVEC6 DTVEC5 Initial value : R/(W) * ...
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Item Page Revision (See Manual for Details) 8.2.2 Register 214 Configuration 8.3.2 Register 225 Configuration 8.4.2 Register 230 Configuration 8.5.2 Register 235 Configuration 8.6.2 Register 237 Configuration Rev.3.00 Mar. 26, 2007 Page xii of xlii REJ09B0355-0300 Port 1 Data Direction ...
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Item Page Revision (See Manual for Details) 8.7.2 Register 241 Configuration 8.8.2 Register 248 Configuration 8.9.2 Register 254 Configuration 8.10.2 Register 260 Configuration 8.11.2 Register 266 Configuration 8.12.2 Register 272 Configuration Port A Data Direction Register (PADDR) Description amended ... ...
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Item Page Revision (See Manual for Details) 8.13.2 Register 278 Configuration 8.14 Handling of 283 Unused Pins 9.2.1 Timer Control 294 Register (TCR) 9.2.5 Timer Status 311 Register (TSR) 312 Rev.3.00 Mar. 26, 2007 Page xiv of xlii REJ09B0355-0300 Port ...
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Item Page Revision (See Manual for Details) 9.2.5 Timer Status 312 Register (TSR) 9.7 Usage Notes 352 Figure 9.52 Contention 360 between Overflow and Counter Clearing Figure 9.53 Contention 361 between TCNT Write and Overflow 10.2.2 Time Constant 367 Registers ...
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Item Page Revision (See Manual for Details) 10.2.3 Time Constant 367 Registers B0 and B1 (TCORB0, TCORB1) 10.2.5 Timer 370 Control/Status Registers 0 and 1(TCSR0, TCSR1) 371 10.6.1 Setting Module 381 Stop Mode 11.2.2 Timer 391 Control/Status Register (TCSR) 11.2.3 ...
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Item Page Revision (See Manual for Details) 12.2.7 Serial Status 417 Register (SSR) 418 420 Bit 7 Transmit Data Register Empty (TDRE) Note * added [Clearing conditions] When 0 is written to ... When the DTC* is activated by a ...
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Item Page Revision (See Manual for Details) 12.2.8 Bit Rate Register 422 (BRR) Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 423 12.3.2 Operation in 437 Asynchronous Mode Figure 12.4 Sample SCI Initialization Flowchart Figure 12.5 Sample 438 ...
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Item Page Revision (See Manual for Details) 12.3.3 Multiprocessor 447 Communication Function Figure 12.10 Sample Multiprocessor Serial Transmission Flowchart 12.3.4 Operation in 456 Clocked Synchronous Mode Figure 12.16 Sample Serial Transmission Flowchart Figure 12.18 Sample 459 Serial Reception Flowchart Figure ...
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Item Page Revision (See Manual for Details) 12.4 SCI Interrupt 462 12.5 Usage Notes 464 467 467 to 472 13.2.2 Serial Status 479 Register (SSR) Rev.3.00 Mar. 26, 2007 Page xx of xlii REJ09B0355-0300 Note * added When TDRE flag ...
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Item Page Revision (See Manual for Details) 13.2.2 Serial Status 479 Register (SSR) 13.3.4 Register Settings 486 13.3.6 Data Transfer 495 Operations 496 497 Note * added Notes: etu: ... * DTC can clear this bit only when DISEL is ...
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Item Page Revision (See Manual for Details) 13.4 Usage Notes 500 501 14.1.1 Features 503 14.2.2 A/D 508 Control/Status Register (ADCSR) 509 14.4.1 Single Mode 514 (SCAN = 0) Figure 14.3 Example of A/D Converter Operation (Single Mode, Channel 1 ...
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Item Page Revision (See Manual for Details) 14.4.3 Input Sampling 517 and A/D Conversion Time Figure 14.5 A/D Conversion Timing 14.6 Usage Notes 519 15.2.1 System Control 527 Register (SYSCR) 16.1.1 Block Diagram 530 Figure 16.1 Block Diagram of ROM ...
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Item Page Revision (See Manual for Details) 17.7 Note on Crystal 553 Resonator 18.6.3 Setting 565 Oscillation Stabilization Time after Clearing Software Standby Mode Table 18.4 Oscillation Stabilization Time Settings 18.7.1 Hardware 567 Standby Mode 19.5 A/D Conversion 597 Characteristics ...
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Item Page Revision (See Manual for Details) Appendix B Register 659 Field 662 680 DTVECR H'FF37 DTC Figure amended Bit : SWDTE DTVEC6 DTVEC5 Initial value : R/( R/( R/(W) ...
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Item Page Revision (See Manual for Details) Appendix B Register 681 Field 689 690 698 699 Rev.3.00 Mar. 26, 2007 Page xxvi of xlii REJ09B0355-0300 SSR0 H'FF7C Smart Card Interface 0 Note *2 added 1 2 R/(W)* DTC* Notes: 1. ...
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Item Page Revision (See Manual for Details) Appendix B Register 702 Field 705 707 709 716 ADCSR H'FF98 A/D Converter Note *2 added 1 2 R/(W)* DTC* Notes: 1. Can only be written with 0 for flag clearing. 2. DTC ...
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Item Page Revision (See Manual for Details) Appendix B Register 722 Field 728 Appendix H Package 771 Dimensions Figure H.1 FP-100B Package Dimensions Figure H.2 TFP-100B 772 Package Dimensions All trademarks and registered trademarks are the property of their respective ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Internal Block Diagram..................................................................................................... 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... 12 Section 2 CPU ...................................................................................................................... 19 2.1 Overview........................................................................................................................... 19 2.1.1 Features................................................................................................................ ...
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Program Execution State...................................................................................... 61 2.8.5 Bus-Released State............................................................................................... 61 2.8.6 Power-Down State ............................................................................................... 61 2.9 Basic Timing..................................................................................................................... 62 2.9.1 Overview.............................................................................................................. 62 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 62 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 64 2.9.4 External Address Space ...
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Interrupts after Reset............................................................................................ 98 4.2.5 State of On-Chip Supporting Modules after Reset Release ................................. 98 4.3 Interrupts ........................................................................................................................... 99 4.4 Trap Instruction................................................................................................................. 100 4.5 Stack Status after Exception Handling.............................................................................. 101 4.6 Notes on Use of the Stack ................................................................................................. 102 ...
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Section 6 Bus Controller 6.1 Overview........................................................................................................................... 131 6.1.1 Features................................................................................................................ 131 6.1.2 Block Diagram..................................................................................................... 132 6.1.3 Pin Configuration................................................................................................. 133 6.1.4 Register Configuration......................................................................................... 134 6.2 Register Descriptions ........................................................................................................ 135 6.2.1 Bus Width Control Register (ABWCR)............................................................... 135 6.2.2 Access State Control Register (ASTCR) ...
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Usage Note........................................................................................................... 175 6.9 Bus Arbitration.................................................................................................................. 175 6.9.1 Overview.............................................................................................................. 175 6.9.2 Operation ............................................................................................................. 175 6.9.3 Bus Transfer Timing ............................................................................................ 176 6.9.4 External Bus Release Usage Note........................................................................ 176 6.10 Resets and the Bus Controller ........................................................................................... 176 Section 7 Data Transfer ...
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Port 1................................................................................................................................. 213 8.2.1 Overview.............................................................................................................. 213 8.2.2 Register Configuration......................................................................................... 214 8.2.3 Pin Functions ....................................................................................................... 216 8.3 Port 2................................................................................................................................. 224 8.3.1 Overview.............................................................................................................. 224 8.3.2 Register Configuration......................................................................................... 224 8.3.3 Pin Functions ....................................................................................................... 227 8.4 Port 3................................................................................................................................. 229 8.4.1 Overview.............................................................................................................. 229 8.4.2 ...
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Overview.............................................................................................................. 265 8.11.2 Register Configuration......................................................................................... 266 8.11.3 Pin Functions ....................................................................................................... 268 8.11.4 MOS Input Pull-Up Function............................................................................... 270 8.12 Port F................................................................................................................................. 271 8.12.1 Overview.............................................................................................................. 271 8.12.2 Register Configuration......................................................................................... 272 8.12.3 Pin Functions ....................................................................................................... 274 8.13 Port G ................................................................................................................................ 277 8.13.1 ...
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Interrupts........................................................................................................................... 341 9.5.1 Interrupt Sources and Priorities............................................................................ 341 9.5.2 DTC Activation.................................................................................................... 342 9.5.3 A/D Converter Activation.................................................................................... 342 9.6 Operation Timing.............................................................................................................. 343 9.6.1 Input/Output Timing ............................................................................................ 343 9.6.2 Interrupt Signal Timing ....................................................................................... 348 9.7 Usage Notes ...................................................................................................................... 352 Section 10 ...
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Section 11 Watchdog Timer 11.1 Overview........................................................................................................................... 387 11.1.1 Features................................................................................................................ 387 11.1.2 Block Diagram ..................................................................................................... 388 11.1.3 Pin Configuration................................................................................................. 389 11.1.4 Register Configuration......................................................................................... 389 11.2 Register Descriptions ........................................................................................................ 390 11.2.1 Timer Counter (TCNT)........................................................................................ 390 11.2.2 Timer Control/Status Register (TCSR) ................................................................ 390 ...
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Module Stop Control Register (MSTPCR) .......................................................... 431 12.3 Operation .......................................................................................................................... 432 12.3.1 Overview.............................................................................................................. 432 12.3.2 Operation in Asynchronous Mode ....................................................................... 434 12.3.3 Multiprocessor Communication Function ........................................................... 445 12.3.4 Operation in Clocked Synchronous Mode ........................................................... 453 12.4 SCI Interrupts.................................................................................................................... 462 ...
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Interface to Bus Master ..................................................................................................... 512 14.4 Operation........................................................................................................................... 513 14.4.1 Single Mode (SCAN = 0) .................................................................................... 513 14.4.2 Scan Mode (SCAN = 1) ....................................................................................... 515 14.4.3 Input Sampling and A/D Conversion Time ......................................................... 517 14.4.4 External Trigger Input Timing ...
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Connecting a Crystal Resonator........................................................................... 546 17.3.2 External Clock Input............................................................................................ 548 17.4 Duty Adjustment Circuit................................................................................................... 553 17.5 Medium-Speed Clock Divider .......................................................................................... 553 17.6 Bus Master Clock Selection Circuit.................................................................................. 553 17.7 Note on Crystal Resonator ................................................................................................ 553 Section 18 Power-Down Modes ...
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Appendix A Instruction Set A.1 Instruction List .................................................................................................................. 599 A.2 Operation Code Map......................................................................................................... 623 A.3 Number of States Required for Instruction Execution ...................................................... 627 Appendix B Register Field B.1 Register Addresses ............................................................................................................ 638 B.2 Register Descriptions ........................................................................................................ 644 Appendix C ...
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Rev.3.00 Mar. 26, 2007 Page xlii of xlii REJ09B0355-0300 ...
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Overview The H8S/2245 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas Technology proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with ...
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Section 1 Overview Table 1.1 Overview Item Specification CPU General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations (20-MHz ...
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Item Specification 16-bit timer-pulse 3-channel 16-bit timer on-chip unit (TPU) Pulse I/O processing capability for pins' Automatic 2-phase encoder count capability 8-bit timer 8-bit up-counter (external event count capability) 2 channels Two time constant registers Two-channel connection ...
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Section 1 Overview Item Specification Power-down state Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Operating modes Seven MCU operating modes CPU Operating Mode Mode 1 Normal Advanced Note: ...
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Item Specification Product lineup Mask ROM Version HD6432246 HD6432245 HD6432244 HD6432243 HD6432242 HD6432241R HD6432240 Model ZTAT Version ROM/RAM (Bytes) HD6472246 128 k/8 k — 128 k/4 k — 64 k/8 k — 64 k/4 k — 32 k/8 k — ...
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Section 1 Overview 1.2 Internal Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES WDTOVF NMI HWR PF ...
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Pin Description 1.3.1 Pin Arrangement Figure 1.2 shows the pin arrangement of the H8S/2245 Group. PF /IRQ0/BREQ ref P4 /AN0 /AN1 /AN2 /AN3 ...
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Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 shows the pin functions in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin No. FP-100B, Mode 2 * TFP-100B Mode 1 1 ...
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Pin No. FP-100B, Mode 2 * TFP-100B Mode ...
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Section 1 Overview Pin No. FP-100B, Mode 2 * TFP-100B Mode /TxD2 ...
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Pin No. FP-100B, Mode 2 * TFP-100B Mode /BREQ/ PF /BREQ IRQ0 IRQ0 ref ref 79 P4 /AN0 P4 /AN0 /AN1 P4 /AN1 ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions. Table 1.3 Pin Functions Pin No. Type Symbol FP-100B, TFP-100B Power V 40, 65 18, 31, 49, 68 Clock XTAL 66 EXTAL ...
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Pin No. Type Symbol FP-100B, TFP-100B Operating mode MD to 61, 58 control MD 0 System control RES 62 STBY 64 BREQ 76 BREQO 74 Section 1 Overview I/O Name and Function Input Mode pins: These pins set ...
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Section 1 Overview Pin No. Type Symbol FP-100B, TFP-100B System control BACK 75 Interrupts NMI 63 IRQ7 to 94, 93, 13, 12, IRQ0 Address bus 100, 99 50, ...
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Pin No. Type Symbol FP-100B, TFP-100B 16-bit timer- TCLKD pulse unit TCLKA (TPU) TIOCA0, 99, 100 TIOCB0, TIOCC0, TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 8-bit timer TMO0, 91, 92 TMO1 ...
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Section 1 Overview Pin No. Type Symbol FP-100B, TFP-100B A/D converter AN3 AN0 ADTRG ref I/O ports 100 ...
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Pin No. Type Symbol FP-100B, TFP-100B I/O ports ...
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Section 1 Overview Rev.3.00 Mar. 26, 2007 Page 18 of 772 REJ09B0355-0300 ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Section 2 CPU High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate: 8/16/32-bit register-register add/subtract (20-MHz operation) 8 8-bit register-register multiply: 16 ÷ 8-bit register-register divide: 16 16-bit register-register multiply: 32 ÷ 16-bit ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit expanded registers, and one 8-bit control registers, have been added. Expanded address space Normal ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area ...
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Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2.2). The exception vector table differs depending ...
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Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored as shown in ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling, they are stored ...
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Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than ...
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Section 2 CPU Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to appendix A.1, Instruction List. Operations can be performed on the CCR bits by the ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Section 2 CPU Data Type General Register Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV 1 POP* , PUSH* 5 LDM* ...
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Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. 5. Only register ER0 to ER6 should be used when using the STM/LDM instruction. 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations ...
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Section 2 CPU Function Instruction System TRAPA — control RTE — SLEEP — LDC B STC — ANDC, ORC, B XORC NOP — Block data transfer — Legend: B: Byte W: Word L: Longword Note: * Cannot be used in ...
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Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in the tables is defined below. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General register* ...
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Section 2 CPU Table 2.3 Data Transfer Instructions 1 Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be ...
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Table 2.4 Arithmetic Operation Instructions 1 Instruction Size* Function ADD B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Immediate byte data cannot be ...
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Section 2 CPU 1 Instruction Size* Function EXTU W/L Rd (zero extension) Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros ...
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Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a general register and ...
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Section 2 CPU Table 2.7 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits ...
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Instruction Size* Function BXOR B C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C Exclusive-ORs the carry flag with the inverse of ...
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Section 2 CPU Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS ...
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Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the source operand contents or immediate ...
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Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfer a data block. Starting from the address set in ER5, transfers data for the number ...
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Basic Instruction Formats The H8S/2245 Group instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.12 ...
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Section 2 CPU 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these ...
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Register Direct—Rn The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers and ...
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Section 2 CPU To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed (H'FFFFFF). For a ...
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Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address ...
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Section 2 CPU Table 2.13 Effective Address Calculation Rev.3.00 Mar. 26, 2007 Page 54 of 772 REJ09B0355-0300 ...
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Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 indicates the state ...
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Section 2 CPU End of bus request Bus-released state End of exception handling Exception-handling state RES = high 1 Reset state * From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. ...
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Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table ...
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Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start ...
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Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than ...
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Section 2 CPU 2.9 Basic Timing 2.9.1 Overview The H8S/2000 CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred "state." The memory ...
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Bus cycle Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.18 Pin States during On-Chip Memory Access T1 Rev.3.00 Mar. 26, 2007 Page 63 of 772 Section 2 CPU REJ09B0355-0300 ...
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Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 ...
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Address bus AS RD HWR, LWR Data bus Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state ...
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Section 2 CPU 2.10 Usage Notes 2.10.1 TAS Instruction Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 Series C/C++ compilers. ...
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The BSET, BCLR, BNOT, BST, and BIST instructions perform their operations in the following order. 1. Read the data in byte units 2. Perform the bit manipulation operation according to the instruction on the data read 3. Write the data ...
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Section 2 CPU The bit manipulation operation is performed on this value that was read. In this example, bit 4 will be cleared for H'F8. P17 P16 I/O Output Output P1DDR 1 After bit 1 manipulation After the bit manipulation ...
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Write data to the work area Write the work area data to the register that includes write-only bits Access the work area data (data transfer and bit manipulation instructions can be used) Write the work area data to the register ...
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Section 2 CPU To switch P14 from being an output pin to being an input pin, we must change the value of P1DDR bit 4 from (H'F0 BCLR #4, @RAM0 P17 P16 I/O Output Output P1DDR 1 ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection Except for the H8S/2240, all H8S/2245 Group products have seven operating modes (modes 1 to 7). The H8S/2240 has three operating modes (modes 1, 4, and 5). These modes ...
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Section 3 MCU Operating Modes The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If ...
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Register Descriptions 3.2.1 Mode Control Register (MDCR) 7 Bit : — Initial value : 1 R/W : — Note: * Determined by pins MD MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2245 ...
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Section 3 MCU Operating Modes Bit 6—Reserved: Read-only bit, always read as 0. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control ...
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Operating Mode Descriptions 3.3.1 Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an ...
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Section 3 MCU Operating Modes 3.3.4 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Pins and ports A, B, and C function as an address bus, ...
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Mode 7 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. Note: Mode 7 cannot be ...
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Section 3 MCU Operating Modes 3.5 Memory Map in Each Operating Mode The H8S/2246, H8S/2245, H8S/2244, H8S/2243, H8S/2242, H8S/2241, and H8S/2240 memory maps are shown in figures 3.1 to 3.7. The address space is 64 kbytes in modes 1 to ...
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E400 On-chip RAM * H'FBFF External address H'FC00 space H'FE3F Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: * External addresses can ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM * 3 H'FFFBFF External address H'FFFC00 space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal ...
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E400 Reserved area * H'EC00 On-chip RAM * H'FBFF External address H'FC00 space H'FE3F Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 Reserved area * 3 H'FFEC00 On-chip RAM * 3 H'FFFBFF External address H'FFFC00 space H'FFFE3F Internal I/O registers H'FFFF08 ...
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E400 On-chip RAM * H'FBFF External address H'FC00 space H'FE3F Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: * External addresses can ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM * 2 H'FFFBFF External address H'FFFC00 space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal ...
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E400 Reserved area * H'EC00 On-chip RAM * H'FBFF External address H'FC00 space H'FE3F Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 Reserved area * 2 H'FFEC00 On-chip RAM * 2 H'FFFBFF External address H'FFFC00 space H'FFFE3F Internal I/O registers H'FFFF08 ...
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E400 On-chip RAM * H'FBFF External address H'FC00 space H'FE3F Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: * External addresses can ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM * 2 H'FFFBFF External address H'FFFC00 space H'FFFE3F Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal ...
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E400 Reserved area * H'EC00 On-chip RAM * H'FBFF External address H'FC00 space H'FE3F Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: ...
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Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 Reserved area * 2 H'FFEC00 On-chip RAM * 2 H'FFFBFF External address H'FFFC00 space H'FFFE3F Internal I/O registers H'FFFF08 ...
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Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'E400 Reserved area * H'EC00 On-chip RAM * H'FBFF External address H'FC00 space H'FE3F Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: ...
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Section 3 MCU Operating Modes Rev.3.00 Mar. 26, 2007 Page 92 of 772 REJ09B0355-0300 ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.3 Exception Sources and Vector Table The exception sources are classified as shown in figure 4.1. Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset ...
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Table 4.2 Exception Vector Table Exception Source Power-on reset Manual reset Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 2 Internal interrupt* Notes: ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2245 Group enters the reset state. A reset initializes the internal state of the ...
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A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. 4.2.3 Reset Sequence The H8S/2245 Group enters the reset state when the RES pin goes low. To ensure ...
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Section 4 Exception Handling RES Address bus RD HWR, LWR (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) ...
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Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 34 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts of each type. The ...
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Section 4 Exception Handling 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address ...
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Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP Figure 4.5 (1) Stack Status after Exception Handling (Normal Modes) SP Figure 4.5 (2) Stack Status after ...
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Section 4 Exception Handling 4.6 Notes on Use of the Stack When accessing word data or longword data, the H8S/2245 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2245 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: Two interrupt control modes Either of two interrupt control modes can be set by ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request WOVI to TEI ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests 5.1.4 Register Configuration Table 5.2 summarizes the registers ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for ...
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Interrupt Control Registers (ICRA to ICRC) Bit : 7 ICR7 ICR6 Initial value : 0 R/W : R/W R/W The ICR registers are three 8-bit readable/writable registers that set the interrupt control level for interrupts other ...
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Section 5 Interrupt Controller 5.2.3 IRQ Enable Register (IER) Bit : 7 IRQ7E IRQ6E Initial value : 0 R/W : R/W R/W IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. IER ...
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The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. The ISCR registers are initialized to H'0000 by a reset and in ...
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Section 5 Interrupt Controller Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF Description 0 [Clearing conditions] Cleared by reading IRQnF flag when IRQnF = ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (34 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be ...
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Section 5 Interrupt Controller IRQn input pin IRQnF Note Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts ...
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Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) Reserved ADI (A/D conversion end) Reserved TGI0A (TGR0A input capture/compare match) TGI0B ...
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Section 5 Interrupt Controller Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) Reserved Rev.3.00 ...
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Interrupt Source CMIA0 (compare match A) CMIB0 (compare match B) OVI0 (overflow 0) Reserved CMIA1 (compare match A) CMIB1 (compare match B) OVI1 (overflow 1) Reserved Reserved ERI0 (receive error 0) RXI0 (reception completed 0) TXI0 (transmit data empty 0) ...
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Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2245 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and ...
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Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control and 3-Level Control Interrupt acceptance control and 3-level mask control is performed by means of ...
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Section 5 Interrupt Controller (2) Default Priority Determination When an interrupt is selected its priority is determined and a vector number is generated. If the same value is set for ICR, acceptance of multiple interrupts is enabled, and so only ...
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Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR, and ICR. Interrupts are enabled when the I bit is cleared ...
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Section 5 Interrupt Controller Control level 1 interrupt? No IRQ0 ? Yes IRQ1 ? Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance Rev.3.00 Mar. 26, 2007 Page 120 of 772 REJ09B0355-0300 Program execution status Interrupt generated? Yes Yes NMI? ...
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Interrupt Control Mode 1 Three-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by means of the I and UI bits in the CPU's CCR, and ICR. Control level 0 interrupt requests are enabled when the ...
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Section 5 Interrupt Controller [ interrupt source occurs when the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, a ...
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Program execution status Interrupt generated? Yes Control level 1 interrupt? Yes No IRQ0? No Yes IRQ1? Yes TEI2? Yes Yes Yes Save PC and CCR I Read vector address Branch to interrupt handling ...
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Section 5 Interrupt Controller 5.4.4 Interrupt Exception Handling Sequence Figure 5.8 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack ...
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Interrupt Response Times The H8S/2245 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5.8 shows ...
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Section 5 Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared disable interrupt requests, the disabling becomes effective after execution of the instruction. In other words, when ...
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Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or ...
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Section 5 Interrupt Controller 5.5.6 NMI Interrupt Usage Notes The NMI interrupt is part of the exception processing performed cooperatively by the LSI's internal interrupt controller and the CPU when the system is operating normally under the specified electrical conditions. ...
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Block Diagram Figure 5.10 shows a block diagram of the DTC and interrupt controller. Interrupt request IRQ interrupt Interrupt source On-chip clear signal supporting module Interrupt controller Figure 5.10 Interrupt Control for DTC 5.6.3 Operation The interrupt controller has ...
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Section 5 Interrupt Controller (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective priorities. ...
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Section 6 Bus Controller 6.1 Overview The H8S/2245 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS3 External bus control signals BREQ BACK BREQO WAIT Legend: ABWCR: Bus width control register ASTCR: Access state control register WCRH: ...
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Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol AS Address strobe RD Read HWR High write LWR Low write CS0 Chip select 0 CS1 Chip select 1 CS2 Chip ...
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Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.2 Bus Controller Registers Name Bus width control register Access state control register Wait control register H Wait control register L Bus control ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 Modes Initial value : 1 R/W : R/W Mode 4 Initial value : 0 R/W : R/W ABWCR is an 8-bit ...
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Section 6 Bus Controller 6.2.2 Access State Control Register (ASTCR) Bit : 7 AST7 AST6 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a ...
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Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area enabled, and bits ...
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Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is ...
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WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space ...
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Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is ...
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Bus Control Register H (BCRH) Bit : 7 ICIS1 ICIS0 Initial value : 1 R/W : R/W BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. ...
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Section 6 Bus Controller Bit 5—Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. In normal mode, the selection can be made from the entire external space. Bit 5 BRSTRM Description 0 Area 0 ...
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Bus Control Register L (BCRL) Bit : 7 BRLE BREQOE Initial value : 0 R/W : R/W BCRL is an 8-bit readable/writable register that performs selection of the external bus release state protocol, selection of the area partition unit ...
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Section 6 Bus Controller Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'01FFFF are to be internal addresses or external addresses. This setting is invalid in normal mode. Bit 5 EAE Description 0 Addresses H'010000 to H'01FFFF are ...
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Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas 128-kbyte or 2-Mbyte units, and performs bus control for external space in area ...
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Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for ...
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Table 6.3 shows the bus specifications for each basic bus interface area. Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH ABWn ASTn Wn1 0 0 — — ...
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Section 6 Bus Controller 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, ...
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Areas in Normal Mode In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space excluding the on-chip RAM and internal I/O ...
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Section 6 Bus Controller 6.3.6 Chip Select Signals The H8S/2245 Group can output chip select signals (CS0 to CS3) to areas the signal being driven low when the corresponding external space area is accessed. In normal mode, ...
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On-Chip Memory (ROM, RAM) Access Timing On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 6.4 shows the on-chip memory access cycle. Figure 6.5 shows the ...
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Section 6 Bus Controller 6.4.2 On-Chip Peripheral Module Access Timing The on-chip peripheral modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure ...
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External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to ...
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Section 6 Bus Controller Byte size 1st bus cycle Word size 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Figure 6.8 Access Sizes and Data Alignment Control (8-Bit Access Space) 16-Bit ...
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Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data bus write, ...
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Section 6 Bus Controller 6.5.4 Basic Timing (1) 8-Bit 2-State Access Space Figure 6.10 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half ( The LWR ...
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Access Space Figure 6.11 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half ( The LWR pin is fixed high. Wait states can ...
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Section 6 Bus Controller (3) 16-Bit 2-State Access Space Figures 6.12 to 6.14 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D lower half ( for ...