FDC37N869 Standard Microsystems, FDC37N869 Datasheet
FDC37N869
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FDC37N869 Summary of contents
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... Forceable Write Protect and Disk Change Controls § Floppy Disk Available on Parallel Port Pins ACPI Compliant § Enhanced Digital Data Separator - 2Mbps, 1 Mbps, 500 Kbps, 300 Kbps, SMSC DS – FDC37N869 Portable Applications FEATURES 250 Kbps Data Rates - Programmable Precompensation Modes § Serial Ports - ...
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... CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS – FDC37N869 Anomaly sheets are available upon request. Page 2 SMSC products are not designed, Rev ...
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... The FDC37N869 does not require any external filter components, is easy to use and offers lower system cost and reduced board area. The FDC37N869 is software and register compatible with SMSC’s proprietary 82077AA core. ...
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... OMMANDS Read Data ................................................................................................................................. 46 Read Deleted Data..................................................................................................................... 48 Read A Track ............................................................................................................................ 48 Write Data................................................................................................................................. 49 Write Deleted Data .................................................................................................................... 50 Verify......................................................................................................................................... 50 Format A Track......................................................................................................................... ....................................................................................................................... 52 ONTROL OMMANDS Read ID..................................................................................................................................... 52 Recalibrate................................................................................................................................ 52 Seek ......................................................................................................................................... 53 Sense Interrupt Status ................................................................................................................ 53 Sense Drive Status.................................................................................................................... 54 Specify ..................................................................................................................................... 54 SMSC DS – FDC37N869 TABLE OF CONTENTS R .................................................................................... 18 EGISTERS Page 4 Rev. 11/09/2000 ...
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... EPP DATA PORT 2.................................................................................................................... 77 EPP DATA PORT 3.................................................................................................................... 77 EPP 1.9 OPERATION .................................................................................................................... 77 Software Constraints................................................................................................................. 78 EPP 1.9 Write............................................................................................................................ 78 EPP 1.9 Read ............................................................................................................................ 78 EPP 1.7 OPERATION .................................................................................................................... 79 Software Constraints................................................................................................................. 79 EPP 1.7 Write............................................................................................................................ 79 EPP 1.7 Read ............................................................................................................................ 79 EXTENDED CAPABILITIES PARALLEL PORT.................................................................................. 81 Vocabulary ............................................................................................................................... 81 ISA IMPLEMENTATION STANDARD.......................................................................................... 82 SMSC DS – FDC37N869 .......................................................................................... 57 ...................................................................................................... 68 O ................................................................................... 70 PERATION T ........................................................................................... 72 IME Page 5 Rev. 11/09/2000 ...
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... CR05....................................................................................................................................... 108 CR06....................................................................................................................................... 108 CR07....................................................................................................................................... 109 CR08....................................................................................................................................... 109 CR09....................................................................................................................................... 109 CR0A ...................................................................................................................................... 110 CR0B ...................................................................................................................................... 110 CR0C ...................................................................................................................................... 111 CR0D ...................................................................................................................................... 111 CR0E ...................................................................................................................................... 111 CR0F....................................................................................................................................... 111 CR10....................................................................................................................................... 112 CR11....................................................................................................................................... 112 CR12 - CR13............................................................................................................................ 112 CR14....................................................................................................................................... 113 CR15....................................................................................................................................... 113 CR16....................................................................................................................................... 113 SMSC DS – FDC37N869 ............................................................................................ 103 Page 6 Rev. 11/09/2000 ...
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... AC TIMING..................................................................................................................................... 126 H T .................................................................................................................................. 126 OST IMING FDD T .................................................................................................................................. 130 IMING ....................................................................................................................... 131 ERIAL ORT IMING ................................................................................................................... 136 ARALLEL ORT IMING Parallel Port EPP Timing......................................................................................................... 137 Parallel Port ECP Timing......................................................................................................... 142 PACKAGE OUTLINES..................................................................................................................... 146 FDC37N869 REVISIONS ................................................................................................................. 147 SMSC DS – FDC37N869 Page 7 Rev. 11/09/2000 ...
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... TXD2 87 nDSR2 88 nRTS2 89 nCTS2 90 nDTR2 91 nADRX/nCLKRUN 92 VSS 93 nDACK_C 94 A10 95 IRQIN 96 DRQ_C 97 IOCHRDY 98 DRVDEN0 99 nMTR0 100 FIGURE 1 - FDC37N869 PIN CONFIGURATION SMSC DS – FDC37N869 PIN CONFIGURATION FDC37N869 100 PIN TQFP Page 8 50 DRQ_B VSS 44 AEN 43 nIOW 42 nIOR ...
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... TC is only accepted when nDACK_x is low and PS/2 model 30 modes active high and in PS/2 mode active low. IO12 Serial IRQ pin used with the CLK33 pin to transfer FDC37N869 interrupts to the host. ICLK 33MHz PCI clock input, used with the SIRQ and the nCLKRUN FDC37N869 interrupts to the host ...
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... Transmit TXD2 Data 2 5 (Note ) 76 Receive RXD1 Data 1 SMSC DS – FDC37N869 BUFFER 6 MODE DESCRIPTION (O12/ This active low high current driver allows current OD12) to flow through the write head. It becomes active just prior to writing to the diskette. (O12/ This active low high current driver provides the OD12) encoded data to the disk drive ...
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... Set nDSR1 Ready nDSR2 83,85 nData nDCD1 Carrier Detect nDCD2 SMSC DS – FDC37N869 BUFFER 6 MODE DESCRIPTION O12 Transmit serial data output for port 1. O6 Active low Request to Send outputs for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR) ...
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... Busy/ BUSY FDC nMotor On 1 nMTR1 SMSC DS – FDC37N869 BUFFER 6 MODE I Active low Ring Indicator inputs for the serial 1 (Note ) port. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR) ...
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... Port Data PD6 6/FDC nMotor On nMTR0 0 61 Port Data 7 PD7 SMSC DS – FDC37N869 BUFFER 6 MODE DESCRIPTION I/OD12 A low active output from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input ...
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... For example, the Buffer Modes for a multiplexed pin with two functions where the primary function is an input and the secondary function is an 8mA bidirectional driver is “I/IO8”. Buffer Modes in parenthesis represent multiple Buffer Modes for a single pin function. SMSC DS – FDC37N869 BUFFER 6 ...
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... Active output drivers in the FDC37N869 will always achieve the minimum specified DC Electrical Characteristics shown in Table 120. Note: If there is a pull- external node driven by an active output driver the FDC37N869 may sink current from the pull-up through the low impedance source. ...
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... RCLOCK RDATA CLOCK GEN nDS0 nINDEX nDIR nMTR0 nTRK0 nSTEP nHDSEL nRDATA nDSKCHG DRVDEN0 nWDATA nWRPRT DRVDEN1 nWGATE FIGURE 2 - FDC37N869 BLOCK DIAGRAM Page 16 nSLCTIN/nSTEP,nINI T/nDIR, nAUTOFD/ nDENSEL, nSTROBE/nDS0, BUSY/nMTR1, MULTI-MODE nACK/nDS1, PARALLEL PE/nWRDATA,nERR PORT/FDC MUX OR/nHDSEL, PD0/nINDEX, PD1/nTRK0, PD2/nWRTPRT, PD3/nRDATA, PD4/nDSKCHG, ...
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... Base +[400:403] for ECP Note 1: Configuration registers can only be modified in the configuration state, refer to section CONFIGURATION on page 101 for more information. All logical blocks in the FDC37N869 can operate normally in the Configuration State. Note 2: The base addresses must be set in the configuration registers before accessing the logical device blocks ...
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... Status Register A (Base Address + 0) monitors the state of the FINTR pin and several disk interface pins in PS/2 interface mode (Table 5) and Model 30 interface mode (Table 6). SRA is read-only and can be accessed at any time when in these modes. During a read in the PC/AT interface mode the data bus pins are held in a high impedance state. SMSC DS – FDC37N869 REGISTER R Status Register A ...
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... Step, Bit 5 Active high status of the STEP output disk interface output pin. nDRV2, Bit 6 The nDRV2 bit is always “1”. Interrupt Pending, Bit 7 Active high bit indicating the state of the Floppy Disk Interrupt output. SMSC DS – FDC37N869 Table 5 - SRA PS/2 Mode ...
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... DIR register, or with a hardware or software reset. DMA Request, Bit 6 Active high status of the DRQ output pin. Interrupt Pending, Bit 7 Active high bit indicating the state of the Floppy Disk Interrupt output. SMSC DS – FDC37N869 Table 6 - SRA PS/2 Model 30 Mode 6 5 ...
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... Drive Select 0, Bit 5 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset unaffected by a software reset. Reserved, Bits Always read as a logic “1”. SMSC DS – FDC37N869 Table 7 - SRB PS/2 Mode ...
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... SELECT 0, Bit 5 Active low status of the DS0 disk interface output. nDRIVE SELECT 1, Bit 6 Active low status of the DS1 disk interface output. nDRV2, Bit 7 The nDRV2 bit is always “1”. SMSC DS – FDC37N869 Table 8 - SRB PS/2 Model 30 Mode nDS0 WDATA F/F RDATA F/F ...
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... The MOTOR ENABLE 2 bit controls the MTR2 disk interface output. A logic “1” in this bit will cause the output pin to go active. MOTOR ENABLE 3, Bit 7 The MOTOR ENABLE 3 bit controls the MTR3 disk interface output. A logic “1” in this bit causes the output to go active. SMSC DS – FDC37N869 Table 9 - Digital Output Register ...
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... In Normal mode the TDR contains only bits 0 and 1 (Table 13). During a read in Normal mode TDR bits are high impedance. The Tape Select Bits are Read/Write. DB7 DB6 TDR Tri-state Tri-state Tri-state Tri-state Tri-state Tri-state SMSC DS – FDC37N869 Table 10 - Drive Activation Values DRIVE DOR VALUE 0 1CH ...
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... RQM DIO DRVx Busy, Bits These bits are set to a “1” when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. SMSC DS – FDC37N869 Table 14 - TDR Enhanced Floppy Mode 2 DB5 DB4 DB3 Drive Type ID ...
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... Table 18 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. The starting track number can be changed using the Configure command. Undefined, Bit 5 Should be written as a logic “0”. SMSC DS – FDC37N869 Table 17 - Data Rate Select Register ...
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... Software Reset, Bit 7 This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. PRECOMP SELECT SMSC DS – FDC37N869 Table 18 - Precompensation Delays PRECOMPENSATION DELAY 0.00 ns-DISABLED 0 1 41. ...
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... Note 1: This is for DENSEL in normal mode (see section CR05 on page 108). The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets. Table 20 - Drive Rate Table (Recommended) DRIVE RATE DRT1 DRT0 Table 21 - Default Precompensation Delays SMSC DS – FDC37N869 Table 19 - Data Rates DATA RATE SEL0 MFM FM IDENT=1 1 1Meg --- 1 0 500 ...
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... The DSK CHG bit monitors the state of the pin of the same name and reflects the opposite value seen on the disk cable. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on page 109). SMSC DS – FDC37N869 Table 22 - Example FIFO Service Delays EXAMPLE DATA RATES 1Mbps ...
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... This bit reflects the value of the NOPREC bit set in the CCR register. DMAEN, Bit 3 This bit reflects the value of DMAEN bit set in the DOR register bit 3. Undefined, Bits Always read as a logic “0” SMSC DS – FDC37N869 Table 24 - DIR PS/2 Interface Mode ...
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... No Precompensation, Bit 2 This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. RESERVED, Bits Bits are RESERVED. Reserved bits cannot be written and return 0 when read. SMSC DS – FDC37N869 ...
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... NW Not Writable 0 MA Missing Address Mark SMSC DS – FDC37N869 Table 28 - Status Register 0 DESCRIPTION 00 - Normal termination of command. properly executed and completed without error Abnormal termination of command. started, but was not successfully completed Invalid command. The requested command could not be executed Abnormal termination caused by Polling. ...
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... Select Reset There are three sources of system reset on the FDC: the RESET pin of the FDC37N869, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. ...
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... The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the SMSC DS – FDC37N869 Page 34 Rev. 11/09/2000 ...
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... The generation of FINT determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. SMSC DS – FDC37N869 Page 35 Rev. 11/09/2000 ...
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... GPL Gap Length H/HDS Head Address HLT Head Load Time HUT Head Unload SMSC DS – FDC37N869 DESCRIPTION The currently selected address 255. The pattern to be written in each sector data field during formatting. Designates which drives are Perpendicular Mode Command. A “1” indicates a perpendicular drive. ...
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... RCN Relative Cylinder Number SC Number of Sectors Per Track SMSC DS – FDC37N869 DESCRIPTION for actual delays. Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a “software Reset” (A reset caused by writing to the appropriate bits of either the DSR or DOR) ...
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... SMSC DS – FDC37N869 DESCRIPTION When set to “1”, sectors containing a deleted data address mark will automatically be skipped during the execution of Read Data. If Read Deleted is executed, only sectors with a deleted address mark will be accessed. When set to “0”, the sector is read or written the same as the read and write commands ...
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... PHASE R/W D7 Command Execution Result SMSC DS – FDC37N869 READ DELETED DATA DATA BUS MFM HDS DS1 DS0 - - - - - - - - EOT - - - - - - - - - - - - - - GPL - - - - - - - - - - - - - - DTL - - - - - - - - - - - - - - ST0 - - - - - - - ...
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... PHASE R/W D7 Command Execution Result SMSC DS – FDC37N869 WRITE DELETED DATA DATA BUS MFM HDS DS1 - - - - - - - - EOT - - - - - - - - - - - - - - GPL - - - - - - - - - - - - - - DTL - - - - - - - - - - - - - - ST0 - - - - - - - ...
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... Command Execution Result PHASE R/W D7 Command W 0 Result R 1 SMSC DS – FDC37N869 READ A TRACK DATA BUS VERIFY DATA BUS MFM HDS DS1 - - - - - - - - ...
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... Execution for W Each Sector Repeat Result PHASE R/W D7 Command Execution SMSC DS – FDC37N869 FORMAT A TRACK DATA BUS MFM HDS DS1 - - - - - - - - GPL - - - - - - - - - - - - - - - ...
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... HLT - - - - - - PHASE R/W D7 Command Result R PHASE R/W D7 Command Execution PHASE R/W D7 Command Execution W SMSC DS – FDC37N869 SENSE INTERRUPT STATUS DATA BUS ST0 - - - - - - - - - - - - - - PCN - - - - - - - SPECIFY ...
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... PHASE R/W D7 Command PHASE R/W D7 Command W 0 Execution Result LOCK SMSC DS – FDC37N869 RELATIVE SEEK DATA BUS DIR HDS DS1 - - - - - - - RCN - - - - - - - DUMPREG DATA BUS PCN-Drive ...
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... PHASE R/W D7 Command Execution Result PHASE R/W D7 Command SMSC DS – FDC37N869 READ ID DATA BUS MFM HDS DS1 - - - - - - - - ST0 - - - - - - - - - - - - - - - - ST1 - - - - - - - - - - - - - - - - ST2 - - - - - - - - - - - - - - - - PERPENDICULAR MODE DATA BUS ...
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... INVALID CODES DATA BUS Invalid Codes - - - - - - - - - - - - ST0 - - - - - - - LOCK DATA BUS LOCK 0 Page 46 REMARKS D0 Invalid Command Codes (NoOp - FDC37N869 goes into Standby State) ST0 = 80H REMARKS Command Codes Rev. 11/09/2000 ...
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... Table 36 - Skip Bit vs. Read Data Command DATA ADDRESS MARK TYPE SK BIT VALUE ENCOUNTERED 0 Normal Data 0 Deleted Data 1 Normal Data 1 Deleted Data SMSC DS – FDC37N869 Table 34 - Sector Sizes N SECTOR SIZE 00 128 bytes 01 256 bytes 02 512 bytes 03 1024 bytes .. ... 07 16 Kbytes Table 35 - Affects of MT and N Bits ...
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... ID Address Mark on the diskette after the second occurrence of a pulse on the IDX pin, then it sets the IC code in Status Register 0 to “01” (abnormal termination), sets the MA bit in Status Register 1 to “1”, and terminates the command. SMSC DS – FDC37N869 MARK TYPE SECTOR ...
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... Please refer to the Read Data Command for details: Transfer Capacity EN (End of Cylinder) bit ND (No Data) bit Head Load, Unload Time Interval ID information when the host terminates the command Definition of DTL when and when N does not = 0 SMSC DS – FDC37N869 Table 38 - Result Phase Table HOST ID INFORMATION AT RESULT PHASE ...
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... SC > # Sectors Remaining OR EOT > # Sectors Per Side Note set to “1” and the SC value is greater than the number of remaining formatted sectors on Side 0, verifying will continue on Side 1 of the disk. SMSC DS – FDC37N869 SC/EOT VALUE TERMINATION RESULT Success Termination Result Phase Valid ...
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... IAM GAP 40x 6x 26x GAP4 SYN IAM GAP 80x 12x 50x SMSC DS – FDC37N869 Table 40 - FORMAT FIELDS SYSTEM 34 (DOUBLE DENSITY) FORMAT SYN IDAM GAP SYN 12x 22x ...
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... Recalibrate command to return the head back to physical Track 0. The Recalibrate command does not have a result phase. command must be issued after the Recalibrate command to effectively terminate it and to provide verification of the SMSC DS – FDC37N869 Table 41 - Typical Values for Formatting SECTOR SIZE ...
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... FDC requires a data transfer during the execution phase in the non-DMA mode The Sense Interrupt Status command resets the interrupt signal and, via the IC code and SE bit of Status Register 0, identifies the cause of the interrupt SMSC DS – FDC37N869 Table 42 - Interrupt Identification IC INTERRUPT DUE TO 11 Polling 00 ...
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... Defaults to no implied seek. EFIFO - A “1” disables the FIFO (default). This means data transfers are asked for on a byte-by-byte basis. Defaults to “1”, FIFO disabled. The threshold defaults to “1”. SMSC DS – FDC37N869 Table 43 - Drive Control Delays (ms) HUT ...
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... This may require the host to issue a Read ID command to ensure that the head is physically on the track that software assumes it to be. Different FDC commands will return different cylinder results which may be difficult to keep track of with software without the Read ID command. SMSC DS – FDC37N869 Table 44 - Head Step Direction Control DIR ...
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... For D0-D3 programmed to “0” for conventional mode drives any data written will be at the currently programmed write pre-compensation. Note: Bits D0-D3 can only be overwritten when OW is programmed as a “1”. If either GAP or WGATE is a “1” then D0-D3 are ignored. SMSC DS – FDC37N869 Page 56 Rev. 11/09/2000 ...
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... COMPATIBILITY The FDC37N869 was designed with software compatibility in mind fully backwards-compatible solution with the older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the IDENT and MFM bits are configured by the system BIOS ...
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... Parallel Port controller. For example, if the FDC is enabled onto the Parallel Port the multiplexed FDD Interface should function normally regardless of the Parallel Port Power control CR01.2. Table 47 illustrates this functionality. PARALLEL PARALLEL PORT FDC PORT POWER CR01.2 CR04 SMSC DS – FDC37N869 Table 46 - FDC Parallel Port Pins SPP MODE PIN DIRECTION nSTB I/O PD0 I/O PD1 I/O PD2 ...
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... The Parallel Port Control register reads as “Cable Not Connected” when the PP FDC is enabled; i.e., STROBE = AUTOFD = SLC = 0 and nINIT = 1 SERIAL PORT (UART) The FDC37N869 incorporates two full function UARTs. They are compatible with the NS16450, the 16450 ACE registers and the NS16550A. The UARTs perform serial-to-parallel conversion on received characters and parallel-to-serial conversion on transmit characters. The data rates are independently programmable from 115.2K baud down to 50 baud. The character options are programmable for 1 start ...
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... Serial Port interrupt out of the FDC37N869. All other system functions operate in their normal manner, including the Line Status and MODEM Status Registers. The contents of the Interrupt Enable Register are described below. ERDAI, Bit 0 The ERDAI bit enables the Received Data Available Interrupt (and time-out interrupts in the FIFO mode) when set to logic “ ...
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... SMSC DS – FDC37N869 Table 49 - Interrupt Control INTERRUPT SET AND RESET FUNCTIONS PRIORITY INTERRUPT INTERRUPT LEVEL TYPE SOURCE - None None Highest Receiver Overrun Error, Line Status Parity Error, Framing Error or Break Interrupt ...
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... Bits are RESERVED. Reserved bits cannot be written and return 0 when read. RCVR Trigger, Bits The RCVR Trigger bits are used to set the trigger level for the RCVR FIFO interrupt (Table 50). TRIGGER Bit SMSC DS – FDC37N869 Table 50 - RCVR Trigger Encoding RCVR RCVR FIFO Trigger Level (BYTES) Bit ...
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... When the Set Break Control bit is a logic “1”, the transmit data output (TXD) is forced to the Spacing or logic “0” state and remains there until reset by a low level bit 6, regardless of other transmitter activity. This feature enables the Serial Port to alert a terminal in a communications system. SMSC DS – FDC37N869 Table 51 - Word Length Encoding WORD LENGTH ...
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... MODEM Control Register instead of the MODEM Control inputs. The interrupts are still controlled by the Interrupt Enable Register. Reserved, Bits Bits are RESERVED. Reserved bits cannot be written and return 0 when read. SMSC DS – FDC37N869 Page 64 Rev. 11/09/2000 ...
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... Transmitter Holding Register into the Transmitter Shift Register. The bit is reset to logic “0” whenever the CPU loads the Transmitter Holding Register. In the FIFO mode this bit is set when the XMIT FIFO is empty cleared when at least 1 byte is written to the XMIT FIFO. Bit 5 is read-only. SMSC DS – FDC37N869 Page 65 Rev. 11/09/2000 ...
Page 66
... OUT1 in the MCR. Data Carrier Detect, Bit 7 The Data Carrier Detect bit is the complement of the Data Carrier Detect input (nDCD). If the Loop bit of the MCR is set to logic “1”, this bit is equivalent to OUT2 in the MCR. SMSC DS – FDC37N869 Page 66 Rev. 11/09/2000 ...
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... SMSC DS – FDC37N869 PERCENT ERROR DIFFERENCE BETWEEN DESIRED AND ACTUAL* 2307 0.03 1538 0.03 1049 0.005 858 0.01 769 0.03 384 0.16 192 0.16 96 0.16 64 0. ...
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... When a time-out interrupt has occurred it is cleared and the timer reset when the CPU reads one character from the RCVR FIFO. 5. When a time-out interrupt has not occurred the time-out timer is reset after a new character is received or after the CPU reads the RCVR FIFO. SMSC DS – FDC37N869 Table 54 - RESET Function RESET CONTROL RESET All bits low RESET Bit 0 is high ...
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... Line Control Register ADDR = 4 MODEM Control Register ADDR = 5 Line Status Register ADDR = 6 MODEM Status Register ADDR = 7 Scratch Register (Note 4) ADDR = 0 Divisor Latch (LS) DLAB = 1 SMSC DS – FDC37N869 REGISTER SYMBOL BIT 0 RBR Data Bit 0 (Note 1) THR Data Bit 0 IER Enable Received Data Available Interrupt ...
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... Note 5: These bits are always zero in the non-FIFO mode. Note 6: Writing a one to this bit has no effect. DMA modes are not supported in this chip. Notes On Serial Port FIFO Mode Operation GENERAL The RCVR FIFO will hold bytes regardless of which trigger level is selected. SMSC DS – FDC37N869 REGISTER SYMBOL BIT 0 DLM ...
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... INFRARED INTERFACE The FDC37N869 infrared interface provides a two-way wireless communications port using infrared as the transmission medium. Several infrared protocols have been provided in this implementation including IrDA v1.1 (SIR/FIR), ASKIR, and Consumer IR (Figure 3). For more information consult the SMSC Infrared Communication Controller (IRCC) specification ...
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... One uses a mode pin (IR Mode) to program the data rate, while the other has a second Rx data pin (IRR3). The FDC37N869 uses Pin 21 for these functions. Pin 21 has IR Mode and IRR3 as its first and second alternate function, respectively. These functions are selected through CR29 as shown in Table 57 ...
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... IrCC Block RAW COM TV ASK OUT MUX IrDA FIR AUX COM G.P. Data Fast Bit FIGURE 3 - INFRARED INTERFACE BLOCK DIAGRAM SMSC DS – FDC37N869 TX1 0 RX1 1 1 TX2 1 RX2 TX3 RX3 IR MODE FAST Page 73 TXD2 RXD2 IRTX2 IRRX2 IR Mode /IRR3 Rev. 11/09/2000 ...
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... PARALLEL PORT The FDC37N869 incorporates an IBM XT/AT compatible parallel port. The FDC37N869 supports the optional PS/2 type bi-directional parallel port (SPP), the Enhanced Parallel Port (EPP) and the Extended Capabilities Port (ECP) parallel port modes. Refer to the FDC37N869 Configuration Registers and the following hardware configuration description for information on disabling, powering down, changing the base address, and selecting the mode of operation of the parallel port ...
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... BIT 3 nERR - nERROR The level on the nERROR input is read by the CPU as bit 3 of the Printer Status Register. A logic “0” means an error has been detected; a logic “1” means no error has been detected. SMSC DS – FDC37N869 Table 60 - Parallel Port Connector STANDARD ...
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... Parallel Control Direction is valid in extended mode only (CR#1<3>=0). In printer mode, the direction is always out regardless of the state of this bit. In bi-directional mode, a logic “0” means that the printer port is in output mode (write); a logic “1” means that the printer port is in input mode (read). SMSC DS – FDC37N869 Page 76 When the ...
Page 77
... If a time-out occurs, the current EPP cycle is aborted and the time-out condition is indicated in Status bit 0. During an EPP cycle, if STROBE is active, it overrides the EPP write signal forcing the PDx bus to always write mode and the nWRITE signal to always be asserted. SMSC DS – FDC37N869 Page 77 Rev. 11/09/2000 ...
Page 78
... Peripheral drives PData bus valid. 7. Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. SMSC DS – FDC37N869 beginning of the termination phase. peripheral should latch the information byte now. Page 78 and the chip may ...
Page 79
... If nWAIT is asserted, IOCHRDY is deasserted until the peripheral deasserts nWAIT or a time-out occurs. 5. The Peripheral drives PData bus valid. 6. The Peripheral deasserts nWAIT, indicating that PData is valid and the chip may begin the termination phase of the cycle. SMSC DS – FDC37N869 Page 79 Rev. 11/09/2000 ...
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... Note 1: SPP and EPP can use 1 common register. Note 2: nWrite is the only EPP output that can be over-ridden by SPP control port during an EPP cycle. For correct EPP read cycles, PCD is required low. SMSC DS – FDC37N869 Table 61 - EPP Pin Descriptions TYPE DESCRIPTION O This signal is active low ...
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... MODE 1 Note : These registers are available in all modes. 2 Note : All FIFOs use one common 16 byte FIFO. SMSC DS – FDC37N869 Table 62 - ECP Registers PD6 PD5 PD4 Address or RLE field nAck PError Select nFault 0 Direction ackIntEn ...
Page 82
... The request is merely a “hint” to the host; the host has ultimate control over the transfer direction. This signal would be typically used to generate an interrupt to the host CPU. SMSC DS – FDC37N869 Table 63 - ECP Pin Descriptions DESCRIPTION The peripheral drives this signal low to acknowledge ...
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... Parallel Port Data FIFO mode 011 ECP Parallel Port mode 100 EPP mode (If this option is enabled in the configuration registers) 101 (Reserved) 110 Test mode 111 Configuration mode SMSC DS – FDC37N869 DESCRIPTION Table 64 - ECP Register Definitions ECP MODES 000-001 011 All All 010 011 110 ...
Page 84
... The Control Register is located at an offset of ‘02H’ from the base address. The Control Register is initialized to zero by the RESET input, bits only being affected; bits 6 and 7 are hard wired low. BIT 0 STROBE - STROBE This bit is inverted and output onto the nSTROBE output. SMSC DS – FDC37N869 Page 84 Rev. 11/09/2000 ...
Page 85
... Reads or DMAs from the FIFO will return bytes of ECP data to the system. tFifo (Test FIFO Mode) ADDRESS OFFSET = 400H Mode = 110 Data bytes may be read, written or DMAed to or from the system to this FIFO in any direction. SMSC DS – FDC37N869 Page 85 Rev. 11/09/2000 ...
Page 86
... The DMA Software Select bits indicate the DMA channel number that has been allocated to the Parallel Port. The channel encoding is shown in Table 66. The DMA Software select bits shadow the ECP DMA Select bits in the ECP Software Select register CR22. SMSC DS – FDC37N869 Page 86 Rev. 11/09/2000 ...
Page 87
... This prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. BIT 3 dmaEn Read/Write 1: Enables DMA (DMA starts when serviceIntr is “0”). 0: Disables DMA unconditionally. SMSC DS – FDC37N869 DMA Software Select DMA (cnfgB) SELECTED D2 D1 ...
Page 88
... All drivers have active pull-ups (push-pull). 111: Configuration Mode. In this mode the confgA, confgB registers are accessible at 0x400 and 0x401. All drivers have active pull-ups (push-pull). SMSC DS – FDC37N869 Table 68 - Extended Control Register MODE Page 88 Rev. 11/09/2000 ...
Page 89
... ECP Mode supports two advanced features to improve the effectiveness of the protocol for some applications. The features are implemented by allowing the transfer of normal 8 bit data or 8 -bit commands (Table 70). When in the forward direction, normal data is transferred when HostAck is high and an 8 bit command is transferred when HostAck is low. SMSC DS – FDC37N869 Page 89 After Rev. 11/09/2000 ...
Page 90
... Table 69 - Forward Channel Commands (HostAck Low) Reverse Channel Commands (PeripAck Low) Data Compression The FDC37N869 supports run length encoded (RLE) decompression in hardware and can transfer compressed data to a peripheral. Run length encoded (RLE) compression in hardware is not supported. To transfer compressed data in ECP mode, the compression count is written to the ecpAFifo and the data byte is written to the ecpDFifo ...
Page 91
... The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when the FIFO becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no more data is required. PDRQ goes SMSC DS – FDC37N869 nd cycle, PDRQ must be kept unasserted until Page 91 Rev ...
Page 92
... FIFO this time the FIFO is empty, it can be completely filled in a single burst, otherwise a minimum of (16-<threshold>) bytes may be written to the FIFO in a single burst. This process is repeated until the last byte is transferred into the FIFO. SMSC DS – FDC37N869 Page 92 Rev. 11/09/2000 ...
Page 93
... If the FDC enters the powerdown state through the auto powerdown mode, wake up will occur after a reset or by access to the specific registers shown below hardware or software reset is used the part will follow the normal reset sequence. If wake up occurs as a result of access through selected registers the FDC37N869 will resume normal operation as if the FDC had never powered-down. ...
Page 94
... Consequently, the behavior of the device pins during powerdown very important. The pins of the FDC37N869 FDC can be divided into two major categories: system interface and floppy disk drive interface. When the FDC is powered down, the floppy disk drive pins are disabled so that no power will be drawn through the part as a result of any voltage applied to the pin within the part’ ...
Page 95
... Table 73 depicts the state of the floppy disk drive interface pins in the powerdown state. Table 72 - State of FDC Interface Pins in Powerdown FDD PINS RDATA DRV2 DSKCHG MOTEN[0:3] DS[0:3} WRDATA HDSEL DENSEL DRATE[0:1] SMSC DS – FDC37N869 STATE IN AUTO POWERDOWN Input Pins IOR Unchanged IOW Unchanged A[0:9] Unchanged D[0:7] Unchanged RESET ...
Page 96
... SERIAL IRQ Introduction The FDC37N869 provides a serial interrupt interface to the host. This scheme adheres to the Serial IRQ Specification for PCI Systems, Version 6.0. The CLK33, SIRQ, and nCLKRUN pins are required for this interface. The Serial IRQ Enable bit D7 in CR29 activates the serial interrupt interface. ...
Page 97
... In Quiet Mode any device may initiate a Start Frame by driving the IRQSER low for one clock while the IRQSER is Idle (FIGURE 4). After driving low for one clock, slaves must immediately tristate IRQSER without at any time driving high. SMSC DS – FDC37N869 IRQ0 FRAME IRQ1 FRAME R ...
Page 98
... IRQSER continuously by initiating a Start Frame at the end of every Stop Frame. IRQSER IRQ/Data Frames Once a Start Frame has been initiated, the FDC37N869 will watch for the rising edge of the Start Pulse and start counting IRQ/Data Frames. Each IRQ/Data Frame has three phases. Each phase takes one PCI clock: Sample phase, Recovery phase, and Turn-around phase ...
Page 99
... System Management Interrupt (nSMI). When using Period 3 for IRQ2 the user should mask off the SMI via the SMI Enable Register. Likewise, when using Period 3 for nSMI the user should not configure any logical devices as using IRQ2. Note: There is no SMI support in the FDC37N869. Stop Cycle Control Once all IRQ/Data Frames have completed, the host controller will terminate IRQSER activity by initiating a Stop Frame ...
Page 100
... The FDC37N869 will not assert nCLKRUN under any conditions if SIRQ_EN is inactive (“0”). The SIRQ_EN bit CR29. The FDC37N869 must not assert nCLKRUN already driven low by the central resource; i.e., the PCI CLOCK GENERATOR in Figure 6. The FDC37N869 must not assert nCLKRUN unless the line has been deasserted for two successive clocks ...
Page 101
... CONFIGURATION The configuration of the FDC37N869 is programmed through hardware selectable Configuration Access Ports that appear when the chip is placed into the configuration state. The FDC37N869 logical device blocks, if enabled, will operate normally in the configuration state. Configuration Access Ports The Configuration Access Ports are the CONFIG PORT, the INDEX PORT, and the DATA PORT (Table 75). The base address of these registers is controlled by the nRTS2/SYSOPT pin (see Table 1) and by the Configuration Port Base Address registers CR12 and CR13 ...
Page 102
... Exiting the Configuration State To exit the configuration state, write one byte of AAH data to the CONFIG PORT. The FDC37N869 will automatically deactivate the Configuration Access Ports following this procedure, at which point configuration register access cannot occur until the configuration state is explicitly re-enabled. ...
Page 103
... DX,AL Configuration Select Register (CSR) The Configuration Select Register can only be accessed when the FDC37N869 is in the configuration state. The CSR is located at the INDEX PORT address and must be initialized with configuration register index before the register can be accessed using the DATA PORT. ...
Page 104
... I/O base address will participate in Plug-and-Play range checking. CR01 CR01 can only be accessed in the configuration state and after the CSR has been initialized to 01H. The default value of this register after power up is 9CH (Table 78). SMSC DS – FDC37N869 DB6 DB5 DB4 ...
Page 105
... To disable the host address registers the logical device’s base address must be set below 100h. Devices that are powered down but still reside at a valid I/O base address will participate in Plug-and-Play range checking. SMSC DS – FDC37N869 Table 78 - CR01 DESCRIPTION Read Only. A read returns “ ...
Page 106
... See NOTE in section CR05 on page 108. 2 Note : Pin 92 (TQFP) is tri-stated at power-up. SMSC DS – FDC37N869 Table 79 - CR02 DESCRIPTION Read Only. A read returns “0” high level on this bit, allows normal operation of the Primary Serial Port (Default). A low level on this bit places the Primary Serial Port into Power Down Mode. Read Only. A read returns “ ...
Page 107
... MHz/12=2 MHz, 2 MHz/16=125 kHz). 4 Note : The function of this bit has been modifi ed from the FDC37C669. This bit’s former function, the selection of the pins for IR receive and transmit, has been moved to CR0A. SMSC DS – FDC37N869 DESCRIPTION Bit 0 If CR1 bit low level then: 0 ...
Page 108
... Note : In the FDC37N869, the behavior of the DRVDEN1 Control CR03.4 depends upon the FDC Output Control CR05.1 (Table 82). If the FDC Output Control is active DRVDEN1 will behave as described in the 669FR; i.e., if CR03 the DRVDEN1 output pin assumes the value of the DRVDEN1 function, if CR03 the DRVDEN1 output pin stays high ...
Page 109
... ADRx Configuration Control Bits D[7:6]. The ADRx Configuration Control Bits configure the ADRx Address Decoder (Table 88). To activate the FDC37N869 nADRx output, the system address bus bits A11 to A4 must match the values programmed in CR08 and CR09 and address bits A12 to A15 must be ‘0000b’. ...
Page 110
... CR0B indicates the Drive Rate table used for each drive (see Table 20). Refer to section CR1F on page 114 for the Drive Type register. FDD3 D7 D6 DRT1 DRT0 DRT1 SMSC DS – FDC37N869 Reserved ADRA11 Table 88 - ADRx Configuration Bits ADRx CONTROL ...
Page 111
... CR0D CR0D can only be accessed in the configuration state and after the CSR has been initialized to 0DH. This register is read only. CR0D contains the FDC37N869 Device ID. The default value of this register after power up is 29H. CR0E CR0E can only be accessed in the configuration state and after the CSR has been initialized to 0EH. This register is read only ...
Page 112
... CR12 - CR13 CR12 and CR13 are the FDC37N869 Configuration Ports base address registers (Table 96). These registers are used to relocate the Configuration Ports base address beyond the power-up defaults determined by the SYSOP pin programming. CR12 contains the Configuration Ports base address bits A[7:0]. CR13 contains the Configuration Ports base address bits A[10:8]. The Configuration Ports base address is relocatable on even-byte boundaries ...
Page 113
... CR1 7 R/W RESERVED Note: The controls in the Force FDD Status Change register (CR17) apply to the FDD Interface pins as well as to the Parallel Port FDC. SMSC DS – FDC37N869 CONFIGURATION PORTS BASE ADDRESS VCC POR D7 D6 SYSOP=0: 0xF0 A7 A6 SYSOP=1: 0x70 SYSOP=0: 0x03 “ ...
Page 114
... CR1F indicates the floppy disk Drive Type for each of four floppy disk drives. The floppy disk Drive Type is used to map the three FDC DENSEL, DRATE1 and DRATE0 outputs onto two Super I/O output pins DRVDEN1 and DRVDEN0 (Table 104). SMSC DS – FDC37N869 Table 101 - CR1E DB5 ...
Page 115
... To disable the parallel port, set ADR9 and ADR8 to zero. Parallel Port Address Decoding: nCS = ’0’ and A10 = ’0’ are required to access the Parallel Port when in Compatible, Bi-directional, or EPP modes. A10 is active when in ECP mode. SMSC DS – FDC37N869 Table 103 - CR1F FDD2 ...
Page 116
... CR26 is used to select the DMA for the FDC (Bits and the Parallel Port (bits 0 - 3). Any unselected DMA Request output (DRQ tristate. Table 111 - CR26: FDC and PP DMA Selection Register SMSC DS – FDC37N869 DB5 DB4 ...
Page 117
... CR28 is used to select the IRQ for Serial Port 1 (bits and for Serial Port 2 (bits 3 - 0). Refer to the IRQ encoding for CR27 (Table 113). Any unselected IRQ output (registers CR27 - CR29 tristate. Shared IRQs are not supported in the FDC37N869. UART1 ...
Page 118
... SCE (FIR). Bits D[7:4] are Reserved. Reserved bits cannot be written and return 0 when read. Any unselected DMA Request output (DRQ tristate. Table 116 - CR2C: SCE (FIR) DMA Select Register SMSC DS – FDC37N869 Table 114 - CR29 DESCRIPTION Selects the IRQ for IRQIN See FIGURE 3 – ...
Page 119
... CR2F can only be accessed in the configuration state and after the CSR has been initialized to 2FH. The default value of this register after power up is 00H (Table 119). CR2F is directly connected to SCE Register Block Three, Address 0x06 in the IRCC v2.0 block. D7 CR2F R/W SMSC DS – FDC37N869 Table 117 - CR2D HALF DUPLEX TIME-OUT ...
Page 120
... AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists suggested that a clamp circuit be used. DC ELECTRICAL CHARACTERISTICS (T = 0°C - 70° +3.3 V ± 10 Refer to Table 120 on the following page. SMSC DS – FDC37N869 Page 120 + +150 ...
Page 121
... O12 Type Buffer Low Output Level High Output Level Output Leakage O12PD Type Buffer Low Output Level High Output Level Output Leakage O6 Type Buffer Low Output Level High Output Level Output Leakage SMSC DS – FDC37N869 = 0°C - 70° SYMBOL MIN TYP MAX V 0.8 ILI V 2.0 ...
Page 122
... PWRGD pin. Note 2: Output leakage is measured with the low driving output off, either for a high level output or a high impedance state defined by PWRGD. Note 3: Defined by the device configuration with the PWRGD input low. SMSC DS – FDC37N869 = 0°C - 70° SYMBOL ...
Page 123
... Low Output Level High Output Level Output Leakage O12 Type Buffer Low Output Level High Output Level Output Leakage O12PD Type Buffer Low Output Level High Output Level Output Leakage SMSC DS – FDC37N869 = 0°C - 70° SYMBOL MIN TYP MAX V 0.8 ILI V 2 ...
Page 124
... O4 Type Buffer Low Output Level High Output Level Output Leakage OD12 Type Buffer Low Output Level Output Leakage Supply Current Active Supply Current Standby ChiProtect (nSLCTIN, nINIT, nAUTOFD, nSTROBE, PD[7:0]) SMSC DS – FDC37N869 = 0°C - 70° SYMBOL MIN TYP MAX V 0 2.4 OH ...
Page 125
... SIGNAL NAME SD[0:7] IOCHRDY IRQs DRQs nWGATE nWDATA nHDSEL nDIR nSTEP nDS[1:0] nMTR[1:0] DRVDEN[1:0] TXD nRTS nDTR PD[7:0] nSLCTIN nINIT nALF nSTB SMSC DS – FDC37N869 = 3.3V CC Table 122 - Clock Pin Loading LIMITS SYMBOL MIN TYP MAX OUT TOTAL CAPACITANCE (pF) 240 240 ...
Page 126
... Data to Float Delay from nIOR High t6 Parallel Port Setup Read Strobe to Clear FINTR t7 t8 nIOR or nIOW Inactive for Transfers to and from ECP FIFO t9 nIOR Active to PINTR Inactive FIGURE 8 - MICROPROCESSOR READ TIMING SMSC DS – FDC37N869 AC TIMING DATA VALID t8 t9 min 40 ...
Page 127
... Width t3 A0-A9, AEN, nIOCS16 Hold from nIOW High Data Set Up Time to nIOW High t4 t5 Data Hold Time from nIOW High t6 Write Strobe to Clear FINTR t7 nIOW Inactive to PINTR Inactive SMSC DS – FDC37N869 t2 t4 DATA VALID Parameter min 40 150 FIGURE 9 - MICROPROCESSOR WRITE TIMING ...
Page 128
... Set Up to nIOW/nIOR Low t12 nDACK Hold After nIOW/nIOR High t13 TC Pulse Width t14 AEN Set Up to nIOR/nIOW t15 AEN Hold from nDACK t16 TC Active to PDRQ Inactive SMSC DS – FDC37N869 t16 t11 DATA VALID t13 ...
Page 129
... Clock Cycle Time for 32kHz t1 Clock High Time/Low Time for 32kHz t2 Clock Rise Time/Fall Time (not shown) t4 nRESET Low Time The nRESET low time is dependent upon the processor clock. The nRESET must be active for a minimum of 1.5us. SMSC DS – FDC37N869 min typ 70 35 31.25 16 ...
Page 130
... Active Time Low t8 nWDATA Write Data Width Low t9 nDS0-1, MTR0-1 from End of nIOW *X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz) WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz) SMSC DS – FDC37N869 ...
Page 131
... IRQx Active Delay from nCTSx, nDSRx, nDCDx t3 IRQx Inactive Delay from nIOR (Leading Edge) t4 IRQx Inactive Delay from nIOW (Trailing Edge) t5 IRQx Inactive Delay from nIOW t6 IRQx Active Delay from nRIx SMSC DS – FDC37N869 min 10 FIGURE 13 - SERIAL PORT TIMING Page 131 t6 typ ...
Page 132
... Bit Time at 4.8kbaud t2 Bit Time at 2.4kbaud Notes: 1. Receive Pulse Detection Criteria: A received pulse is considered detected if the received pulse is a minimum of 1.41µs. 2. IRRX: CRC Bit RCV active low nIRRX: CRC Bit RCV active high (default) SMSC DS – FDC37N869 min 1 ...
Page 133
... Bit Time at 4.8kbaud t2 Bit Time at 2.4kbaud Notes: 1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX. 2. IRTX: CRC Bit XMIT active low (default) nIRTX: CRC Bit XMIT active high SMSC DS – FDC37N869 min 1 ...
Page 134
... Modulated Output "On" t6 Modulated Output "On" Notes: 1. IRRX: CRC Bit RCV active low nIRRX: CRC Bit RCV active high (default) MIRRX, nMIRRX are the modulated outputs FIGURE 16 - AMPLITUDE SHIFT KEYED IR RECEIVE TIMING SMSC DS – FDC37N869 min 0.8 ...
Page 135
... Modulated Output "On" t6 Modulated Output "On" Notes: 1. IRTX: CRC Bit XMIT active low (default) nIRTX: CRC Bit XMIT active high MIRTX, nMIRTX are the modulated outputs FIGURE 17 - AMPLITUDE SHIFT KEYED IR TRANSMIT TIMING SMSC DS – FDC37N869 min 0.8 ...
Page 136
... PINTR Delay from nACK, nFAULT t3 PINTR Active Low in ECP and EPP Modes PINTR Delay from nACK t4 nERROR Active to PINTR Active t5 PD0-PD7 Delay from nIOW Active t6 PINTR is the interrupt assigned to the Parallel Port SMSC DS – FDC37N869 min 200 FIGURE 18 - PARALLEL PORT TIMING Page 136 t1 ...
Page 137
... Asserted to nWRITE Asserted NOTE: WAIT must be filtered to compensate for ringing on the parallel bus cable. WAIT is considered to have settled after it does not transition for a minimum of 50 nsec. FIGURE 19 - EPP 1.9 DATA OR ADDRESS WRITE CYCLE SMSC DS – FDC37N869 t18 t9 t12 t11 t4 t15 ...
Page 138
... PD<7:0> t28 t14 DATASTB ADDRSTB nWAIT Timing parameter table for the EPP Data or Address Read Cycle is found on next page. FIGURE 20 - EPP 1.9 DATA OR ADDRESS READ CYCLE SMSC DS – FDC37N869 t11 t13 t18 t10 PData bus driven t5 by peripheral t1 t3 t15 ...
Page 139
... NOTES: 1. nWAIT is considered to have settled after it does not transition for a minimum of 50 ns. 2. When not executing a write cycle, EPP nWRITE is inactive high true only FIGURE 21 - EPP 1.9 DATA OR ADDRESS READ CYCLE TIMING PARAMETERS SMSC DS – FDC37N869 min max units 30 0 ...
Page 140
... Command Deasserted to nWAIT Deasserted NOTES: 1. WRITE is controlled by clearing the PDIR bit to "0" in the control register before performing an EPP Write. 2. This number is only valid if WAIT is active when nIOW goes active. FIGURE 22 - EPP 1.7 DATA OR ADDRESS WRITE CYCLE SMSC DS – FDC37N869 t6 t12 t10 t20 t11 ...
Page 141
... Deasserted to nIOW or nIOR Asserted t22 nIOR Asserted to Command Asserted t23 NOTE: 1. nWRITE is controlled by setting the PDIR bit to "1" in the control register before performing an EPP Read. FIGURE 23 - EPP 1.7 DATA OR ADDRESS READ CYCLE SMSC DS – FDC37N869 t15 t11 t13 t 3 t10 t5 min ...
Page 142
... IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.14, July. 14, 1993, available from Microsoft. The dynamic driver change must be implemented properly to prevent glitching the outputs. SMSC DS – FDC37N869 Page 142 The host then sets HostClk Rev. 11/09/2000 ...
Page 143
... BUSY Inactive to nSTROBE Active t6 BUSY Inactive to PDATE Invalid NOTE: 1. The data is held until BUSY goes inactive or for time t3, whichever is longer. This only applies if another data transfer is pending other data transfer is pending, the data is held indefinitely. SMSC DS – FDC37N869 Parameter min 600 ...
Page 144
... Asserted to nSTROBE Deasserted NOTES: 1. Maximum value only applies if there is data in the FIFO waiting to be written out. 2. BUSY is not considered asserted or deasserted until it is stable for a minimum 130 ns. FIGURE 25 - ECP PARALLEL PORT FORWARD TIMING SMSC DS – FDC37N869 ...
Page 145
... Maximum value only applies if there is room in the FIFO and a terminal count has not been received. ECP can stall by keeping nAUTOFD low. 2. nACK is not considered asserted or deasserted until it is stable for a minimum 130 ns. FIGURE 26 - ECP PARALLEL PORT REVERSE TIMING SMSC DS – FDC37N869 ...
Page 146
... Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25mm per side. 4 Dimension for foot length L are measured at the gauge plane 0.25mm above the seating plane. 5 Details of pin 1 identifier are optional but must be located within the zone indicated. 6. Controlling dimension: millimeter FIGURE 27 - 100 PIN TQFP PACKAGE OUTLINE SMSC DS – FDC37N869 D1/4 E1/4 ...
Page 147
... PAGE(S) SECTION/FIGURE/ENTRY 93 FDC Power Management SMSC DS – FDC37N869 FDC37N869 REVISIONS CORRECTION Note added under this section – see italicized text. Page 147 DATE REVISED 11/09/00 Rev. 11/09/2000 ...