ST72C334 STMicroelectronics, ST72C334 Datasheet
ST72C334
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ST72C334 Summary of contents
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MCU for automotive with single voltage Flash/ROM memory, Memories ■ – Kbyte Program memory (ROM or sin- gle voltage Flash) with readout protection and in-situ programming (remote ISP) – 256 bytes EEPROM Data memory (with read- ...
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... PREAMBLE: ST72C334-Auto VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . 7 2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 REGISTER AND MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3 STRUCTURAL ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4 IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 MEMORY READOUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.2 MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3 MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 ...
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WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 13.4.5Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Clock Managers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet. Please also pay special attention to the Section 6/150 “IMPORTANT NOTES” on page 148 ...
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... PREAMBLE: ST72C334-Auto VERSUS ST72E331 SPECIFICATION New Features available on the ST72C334-Auto 8 or 16K Flash/ROM with In-Situ Programming ■ and Readout protection New ADC with a better accuracy and conversion ■ time New configurable Clock, Reset and Supply ■ system New power saving mode with real-time base: ■ ...
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... ST72124J-Auto devices are for applications that do not need Data EEPROM and the ADC periph- eral. All devices are based on a common industry- standard 8-bit core, featuring an enhanced instruc- tion set. The ST72C334J/N-Auto, ST72C314J/N-Auto and ST72C124J-Auto versions feature single-voltage Figure 1. General Block Diagram RESET ISPSEL V ...
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PIN DESCRIPTION Figure 2. 64-Pin TQFP Package Pinout (N versions) (HS) PE4 (HS) PE5 (HS) PE6 (HS) PE7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 ST72334xx-Auto, ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto PIN DESCRIPTION (Cont’d) Figure 3. 44-Pin TQFP Package Pinout (J versions) PE1 / RDI AIN0 / PD0 AIN1 / PD1 AIN2 / PD2 AIN3 / PD3 AIN4 / PD4 10/150 ...
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PIN DESCRIPTION (Cont’d) For external pin connection guidelines, refer to 108. Legend / Abbreviations for Table Type input output supply Input level Dedicated analog input In/Output level CMOS 0.3V C ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto Pin No. Pin Name SS_3 25 15 PF0/MCO I PF1/BEEP I PF2 I PF4/OCMP1_A I PF6 (HS)/ICAP1_A I/O C ...
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Pin No. Pin Name 61 44 PE0/TDO I PE1/RDI I Notes the interrupt input column, “ei column (wpu) is merged with the interrupt column (int), then the I/O configuration is ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 4 REGISTER AND MEMORY MAP As shown in the Figure 4, the MCU is capable of addressing 64 Kbytes of memories and I/O regis- ters. The available memory locations consist of 128 bytes of register locations, 384 ...
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REGISTER AND MEMORY MAP (Cont’d) Table 2. Hardware Register Map Register Address Block Label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h 0004h PCDR 0005h Port C PCDDR 0006h PCOR 0007h 0008h PBDR 0009h Port B PBDDR 000Ah PBOR ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto Register Address Block Label 002Ah WATCHDOG WDGCR 002Bh CRSR 002Ch Data-EEPROM EECSR 002Dh 0030h 0031h TACR2 0032h TACR1 0033h TASR 0034h TAIC1HR 0035h TAIC1LR 0036h TAOC1HR 0037h TAOC1LR 0038h TIMER A TACHR 0039h TACLR 003Ah TAACHR 003Bh ...
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Register Address Block Label 0070h ADCDR ADC 0071h ADCCSR 0072h to 007Fh Legend: x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configuration, the values of the I/O pins ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 5 FLASH PROGRAM MEMORY 5.1 INTRODUCTION Flash devices have a single voltage non-volatile Flash memory that may be programmed in-situ (or plugged in a programming tool byte-by-byte basis. 5.2 MAIN FEATURES Remote In-Situ Programming (ISP) ...
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DATA EEPROM 6.1 INTRODUCTION The Electrically Erasable Programmable Read Only Memory can be used as a non-volatile back- up for storing data. Using the EEPROM requires a basic access protocol described in this chapter. Figure 6. EEPROM Block Diagram ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto DATA EEPROM (Cont’d) 6.3 MEMORY ACCESS The Data EEPROM memory read/write access modes are controlled by the LAT bit of the EEP- ROM Control/Status register (EECSR). The flow- chart in Figure 7 describes these different memory access ...
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DATA EEPROM (Cont’d) 6.4 POWER SAVING MODES Wait mode The Data EEPROM can enter Wait mode on exe- cution of the WFI instruction of the microcontroller. The Data EEPROM will immediately enter this mode if there is no programming in ...
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... Programming finished or not yet started 1: Programming cycle is in progress Note: if the PGM bit is cleared during the program- ming cycle, the memory data is not guaranteed ST72C334 Flash devices do not have page 145 this protection option RWM PGM 0 ...
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CENTRAL PROCESSING UNIT 7.1 INTRODUCTION This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8-bit data manipulation. 7.2 MAIN FEATURES 63 basic instructions ■ Fast 8-bit by 8-bit multiply ■ 17 main addressing modes ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction ...
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CENTRAL PROCESSING UNIT (Cont’d) Stack Pointer (SP) Read/Write Reset Value: 01 FFh SP7 SP6 SP5 SP4 SP3 The Stack Pointer is a 16-bit register which is al- ways pointing to the next free ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 8 SUPPLY, RESET AND CLOCK MANAGEMENT The ST72334J/N-Auto, ST72314J/N-Auto and ST72124J-Auto microcontrollers include a range of utility features for securing the application in crit- ical situations (for example, in case of a power brown-out), and reducing the ...
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LOW VOLTAGE DETECTOR (LVD) To allow the integration of power management features in the application, the Low Voltage Detec- tor function (LVD) generates a static reset when the V supply voltage is below value. This means ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 8.2 RESET SEQUENCE MANAGER (RSM) 8.2.1 Introduction The reset sequence manager includes three RE- SET sources as shown in Figure External RESET source pulse ■ Internal LVD RESET (Low Voltage Detection) ■ Internal WATCHDOG RESET ■ These ...
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RESET SEQUENCE MANAGER (Cont’d) 8.2.2 Asynchronous External RESET Pin The RESET pin is both an input and an open-drain output with integrated R weak pull-up resistor. ON This pull-up has no fixed value but varies in ac- cordance with the ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 8.3 MULTI-OSCILLATOR (MO) The main clock of the ST7 can be generated by four different source types coming from the multi- oscillator block: an external source ■ 4 crystal or ceramic resonator oscillators ■ an external RC ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 31/150 ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 8.4 CLOCK SECURITY SYSTEM (CSS) The Clock Security System (CSS) protects the ST7 against main clock problems. To allow the in- tegration of the security features in the applica- tions based on a clock filter ...
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SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION Read / Write Reset Value: 000x 000x (xxh) 7 LVD Bit 7:5 = Reserved, always read as 0. Bit 4 = LVDRF LVD reset flag This bit indicates ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 9 INTERRUPTS The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in The maskable ...
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INTERRUPTS (Cont’d) Figure 17. Interrupt Processing Flowchart FROM RESET EXECUTE INSTRUCTION Table 6. Interrupt Mapping Source No. Block RESET Reset TRAP Software Interrupt 0 Not used MCC/RTC Main Clock Controller Time Base Interrupt 1 CSS or Clock Security System Interrupt ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 10 POWER SAVING MODES 10.1 INTRODUCTION To give a large measure of flexibility to the applica- tion in terms of power consumption, four main power saving modes are implemented in the ST7 (see Figure 18): Slow, Wait ...
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POWER SAVING MODES (Cont’d) 10.3 WAIT MODE Wait mode places the MCU in a low power con- sumption mode by stopping the CPU. This power saving mode is selected by calling the WFI instruction. All peripherals remain active. During Wait ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto POWER SAVING MODES (Cont’d) 10.4 ACTIVE HALT AND HALT MODES Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the HALT instruction. The decision to ...
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POWER SAVING MODES (Cont’d) 10.4.2 Halt Mode The Halt mode is the lowest power consumption mode of the MCU entered by executing the HALT instruction when the OIE bit of the Main Clock Controller Status register (MCCSR) is ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 11 I/O PORTS 11.1 INTRODUCTION The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ...
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I/O PORTS (Cont’d) Figure 25. I/O Port General Block Diagram ALTERNATE REGISTER OUTPUT ACCESS ALTERNATE ENABLE DR DDR OR If implemented OR SEL DDR SEL DR SEL 1 0 EXTERNAL INTERRUPT SOURCE ( POLARITY SELECTION Table 7. I/O ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto I/O PORTS (Cont’d) Table 8. I/O Port Configurations NOT IMPLEMENTED TRUE OPEN DRAIN I/O PORTS R PAD NOT IMPLEMENTED IN TRUE OPEN DRAIN V DD I/O PORTS R PAD NOT IMPLEMENTED IN TRUE OPEN ...
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I/O PORTS (Cont’d) CAUTION: The alternate function must not be ac- tivated as long as the pin is configured as input with interrupt, in order to avoid generating spurious interrupts. Analog alternate function When the pin is used as an ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto I/O PORTS (Cont’d) 11.4 LOW POWER MODES Mode Description No effect on I/O ports. External interrupts WAIT cause the device to exit from Wait mode. No effect on I/O ports. External interrupts HALT cause the device to ...
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I/O PORTS (Cont’d) 11.5.1 Register Description DATA REGISTER (DR) Port x Data Register PxDR with Read / Write Reset Value: 0000 0000 (00h Bit 7:0 ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto I/O PORTS (Cont’d) Table 10. I/O Port Register Map and Reset Values Address Register 7 (Hex.) Label Reset Value 0 of all IO port registers 0000h PADR 0001h PADDR MSB 0002h PAOR 1) 0004h PCDR 0005h PCDDR ...
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MISCELLANEOUS REGISTERS The miscellaneous registers allow control over several different features such as the external in- terrupts or the I/O alternate functions. 12.1 I/O PORT INTERRUPT SENSITIVITY The external interrupt sensitivity is controlled by the ISxx bits of the ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto MISCELLANEOUS REGISTERS (Cont’d) 12.3 REGISTERS DESCRIPTION MISCELLANEOUS REGISTER 1 (MISCR1) Read / Write Reset Value: 0000 0000 (00h) 7 IS11 IS10 MCO IS21 IS20 Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using ...
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MISCELLANEOUS REGISTERS (Cont’d) MISCELLANEOUS REGISTER 2 (MISCR2) Read / Write Reset Value: 0000 0000 (00h BC1 BC0 - Bit 7:6 = Reserved Must always be cleared Bit 5:4 = BC[1:0] Beep control These 2 bits select the ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 13 ON-CHIP PERIPHERALS 13.1 WATCHDOG TIMER (WDG) 13.1.1 Introduction The Watchdog timer is used to detect the occur- rence of a software fault, usually generated by ex- ternal interference or by unforeseen logical condi- tions, which causes ...
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WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto WATCHDOG TIMER (Cont’d) Table 13. Watchdog Timer Register Map and Reset Values Address Register 7 (Hex.) Label WDGCR WDGA 002Ah Reset Value 0 52/150 ...
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MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK TIMER (MCC/RTC) The Main Clock Controller consists of three differ- ent functions: a programmable CPU clock prescaler ■ a clock-out signal to supply external devices ■ a real-time clock timer with interrupt capability ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto MAIN CLOCK CONTROLLER WITH REAL-TIME CLOCK TIMER (Cont’d) MISCELLANEOUS REGISTER 1 (MISCR1) See Section 12 on page 47. MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read / Write Reset Value: 0000 0001 (01h TB1 ...
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TIMER 13.3.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths two input sig- nals (input ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) Figure 30. Timer Block Diagram f CPU 8 high EXEDG 1/2 COUNTER 1/4 REGISTER 1/8 ALTERNATE EXTCLK pin COUNTER REGISTER CC[1:0] OVERFLOW DETECT CIRCUIT ICF1 OCF1 TOF ICF2 ICIE OCIE TOIE FOLV2 (See note) ...
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TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). Beginning of the sequence Read MS Byte At t0 Other instructions Returns the buffered Read At t0 +∆t LS Byte value ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) Figure 31. Counter Timing Diagram, internal clock divided by 2 CPU CLOCK INTERNAL RESET TIMER CLOCK COUNTER REGISTER TIMER OVERFLOW FLAG (TOF) Figure 32. Counter Timing Diagram, internal clock divided by 4 CPU CLOCK ...
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TIMER (Cont’d) 13.3.3.3 Input Capture In this section, the index, i, may because there are two input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) Figure 34. Input Capture Block Diagram ICAP1 pin EDGE DETECT CIRCUIT2 ICAP2 pin IC2R Register 16-BIT 16-BIT FREE RUNNING COUNTER Figure 35. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ...
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TIMER (Cont’d) 13.3.3.4 Output Compare In this section, the index, i, may because there are two output compare functions in the 16- bit timer. This function can be used to control an output waveform or ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) Notes: 1. After a processor write cycle to the OCiHR reg- ister, the output compare function is inhibited until the OCiLR register is also written the OCiE bit is not set, the ...
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TIMER (Cont’d) Figure 37. Output Compare Timing Diagram, f INTERNAL CPU CLOCK COUNTER REGISTER OUTPUT COMPARE REGISTER i (OCRi) OUTPUT COMPARE FLAG i (OCFi) OCMPi PIN (OLVLi = 1) Figure 38. Output Compare Timing Diagram, f INTERNAL CPU CLOCK ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) 13.3.3.5 One Pulse Mode One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode ...
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TIMER (Cont’d) Figure 39. One Pulse Mode Timing Example COUNTER ICAP1 OCMP1 Note: IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1 Figure 40. Pulse Width Modulation Mode Timing Example COUNTER 34E2 OCMP1 compare2 Note: OC1R ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) 13.3.3.6 Pulse Width Modulation Mode Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse ...
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TIMER (Cont’d) 13.3.4 Low Power Modes Mode No effect on 16-bit Timer. WAIT Timer interrupts cause the device to exit from Wait mode. 16-bit Timer registers are frozen. In Halt mode, the counter stops counting until Halt mode is ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) 13.3.7 Register Description Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter ...
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TIMER (Cont’d) CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG Bit 7 = OC1E Output Compare 1 Pin Enable. This bit is used only to output the signal ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. 7 ICF1 OCF1 TOF ICF2 OCF2 Bit 7 = ICF1 Input Capture Flag ...
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TIMER (Cont’d) OUTPUT COMPARE 2 (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB OUTPUT COMPARE 2 (OC2LR) Read/Write ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 16-BIT TIMER (Cont’d) Table 16. 16-Bit Timer Register Map and Reset Values Address Register 7 (Hex.) Label Timer A: 32 CR1 ICIE Timer B: 42 Reset Value 0 Timer A: 31 CR2 OC1E Timer B: 41 Reset ...
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SERIAL PERIPHERAL INTERFACE (SPI) 13.4.1 Introduction The Serial Peripheral Interface (SPI) allows full- duplex, synchronous, serial communication with external devices. An SPI system may consist of a master and one or more slaves or a system in which devices ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 42. Serial Peripheral Interface Block Diagram Read Read Buffer MOSI MISO 8-Bit Shift Register Write SCK SS 74/150 Internal Bus DR SPIF WCOL SPIE SPE SPR2 MSTR MASTER CONTROL SERIAL CLOCK GENERATOR ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4 Functional Description Figure 41 shows the serial peripheral interface (SPI) block diagram. This interface contains three dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.2 Slave Configuration In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 and SPR1 bits is not used for the data ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.3 Data Transfer Format During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). The serial clock is used to syn- chronize the data transfer during a sequence of eight ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) Figure 44. Data Clock Timing Diagram SCLK (with CPOL = 1) SCLK (with CPOL = 0) MSBit MISO (from master) MSBit MOSI (from slave) SS (to slave) CAPTURE STROBE CPOL = 1 CPOL ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.4 Write Collision Error A write collision occurs when the software tries to write to the DR register while a data transfer is tak- ing place with an external device. When this hap- pens, the transfer ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.5 Master Mode Fault Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.4.7 Single Master and Multimaster Configurations There are two types of SPI systems: – Single Master System – Multimaster System Single Master System A typical single master system may be configured, using an MCU as the ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.5 Low Power Modes Mode No effect on SPI. WAIT SPI interrupt events cause the device to exit from Wait mode. SPI registers are frozen. HALT In Halt mode, the SPI is inactive. ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) 13.4.7 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0000xxxx (0xh) 7 SPIE SPE SPR2 MSTR CPOL CPHA SPR1 SPR0 Bit 7 = SPIE Serial peripheral interrupt enable. This bit is set and cleared by software. ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) 7 SPIF WCOL - MODF Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer ...
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SERIAL PERIPHERAL INTERFACE (Cont’d) Table 18. SPI Register Map and Reset Values Address Register 7 (Hex.) Label SPIDR MSB 0021h Reset Value x SPICR SPIE 0022h Reset Value 0 SPISR SPIF 0023h Reset Value 0 ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 6 5 ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 13.5 SERIAL COMMUNICATIONS INTERFACE (SCI) 13.5.1 Introduction The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 47. SCI Block Diagram Write Transmit Data Register (TDR) TDO Transmit Shift Register RDI TRANSMIT CONTROL CR2 TIE TCIE RIE SCI INTERRUPT CONTROL TRANSMITTER CLOCK f CPU /16 ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto Read Received Data Register ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.5 Functional Description The block diagram of the Serial Control Interface, is shown in Figure 47. It contains six dedicated registers: – 2 control registers (CR1 and CR2) – A status register (SR) ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.5.2 Transmitter The transmitter can send data words of either bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.5.3 Receiver The SCI can receive data words of either bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) Figure 49. SCI Baud Rate and Extended Prescaler Block Diagram EXTENDED PRESCALER TRANSMITTER RATE CONTROL EXTENDED TRANSMITTER PRESCALER REGISTER EXTENDED RECEIVER PRESCALER REGISTER EXTENDED PRESCALER RECEIVER RATE CONTROL f CPU /PR /16 /2 ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.5.4 Conventional Baud Rate Generation The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: f CPU (32 PR ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.6 Low Power Modes Mode No effect on SCI. WAIT SCI interrupts cause the device to exit from Wait mode. SCI registers are frozen. HALT In Halt mode, the SCI stops transmitting/receiving until Halt mode is ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL COMMUNICATIONS INTERFACE (Cont’d) 13.5.8 Register Description STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) 7 TDRE TC RDRF IDLE OR Bit 7 = TDRE Transmit data register empty. This bit is set by hardware ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined WAKE Bit Receive data bit 8. This bit is used to store the 9th bit of the received word when ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. 7 DR7 DR6 DR5 DR4 DR3 The ...
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SERIAL COMMUNICATIONS INTERFACE (Cont’d) EXTENDED RECEIVE PRESCALER DIVISION REGISTER (ERPR) Read/Write Reset Value: 0000 0000 (00 h) Allows setting of the Extended Prescaler rate divi- sion factor for the receive circuit. 7 ERPR ERPR ERPR ERPR ERPR ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 13.6 8-BIT A/D CONVERTER (ADC) 13.6.1 Introduction The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, successive approximation con- verter with internal sample and hold circuitry. This peripheral has multiplexed analog ...
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A/D CONVERTER (ADC) (Cont’d) 13.6.3.2 Digital A/D Conversion Result The conversion is monotonic, meaning that the re- sult never decreases if the analog input does not and never increases if the analog input does not. If the input voltage ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 8-BIT A/D CONVERTER (ADC) (Cont’d) 13.6.6 Register Description CONTROL/STATUS REGISTER (CSR) Read / Write Reset Value: 0000 0000 (00h) 7 COCO 0 ADON 0 CH3 Bit 7 = COCO Conversion Complete This bit is set by hardware. ...
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A/D CONVERTER (ADC) (Cont’d) Table 20. ADC Register Map and Reset Values Address Register 7 (Hex.) Label ADCDR D7 0070h Reset Value 0 ADCCSR COCO 0071h Reset Value 0 ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 14 INSTRUCTION SET 14.1 ST7 ADDRESSING MODES The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Group Example Inherent nop Immediate ld A,#$55 Direct ld A,$55 Indexed ld ...
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ST7 ADDRESSING MODES (Cont’d) 14.1.1 Inherent All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation. Inherent Instruction NOP No operation TRAP S/W Interrupt Wait For ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto ST7 ADDRESSING MODES (Cont’d) 14.1.6 Indirect Indexed (Short, Long) This is a combination of indirect and short indexed addressing modes. The operand is referenced by its memory address, which is defined by the un- signed addition of ...
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INSTRUCTION GROUPS The ST 7 family devices use an Instruction Set consisting of 63 instructions. The instructions may Group Load and Transfer Stack operation Increment/Decrement Compare and Tests Logical operations Bit Operation Conditional Bit Test and Branch Arithmetic operations ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto INSTRUCTION GROUPS (Cont’d) Mnemo Description ADC Add with Carry ADD Addition AND Logical And BCP Bit compare A, Memory BRES Bit Reset BSET Bit Set BTJF Jump if bit is false (0) BTJT Jump if bit is ...
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INSTRUCTION GROUPS (Cont’d) Mnemo Description JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation POP Pop from the Stack PUSH Push onto the Stack RCF Reset carry ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 15 ELECTRICAL CHARACTERISTICS 15.1 PARAMETER CONDITIONS Unless otherwise specified, all voltages are re- ferred 15.1.1 Minimum and Maximum values Unless otherwise specified the minimum and max- imum values are guaranteed in the worst ...
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ABSOLUTE MAXIMUM RATINGS Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- 15.2.1 Voltage Characteristics Symbol ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto ABSOLUTE MAXIMUM RATINGS (Cont’d) 15.2.3 Thermal Characteristics Symbol T Storage temperature range STG Maximum junction temperature (see T J ING INFORMATION" on page 110/150 Ratings Section 17 "DEVICE CONFIGURATION AND ORDER- 143) Value Unit -65 to +150 ...
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OPERATING CONDITIONS 15.3.1 General Operating Conditions Symbol Parameter V Supply voltage DD f External clock frequency OSC T Ambient temperature range A Figure 54. f Maximum Operating Frequency Versus V OSC f [MHz] OSC 16 FUNCTIONALITY NOT GUARANTEED 12 ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto OPERATING CONDITIONS (Cont’d) 15.3.2 Operating Conditions with Low Voltage Detector (LVD) Subject to general operating conditions for V Symbol Parameter V Reset release threshold (V IT+ Reset generation threshold (V V IT- fall) V LVD voltage threshold ...
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FUNCTIONAL OPERATING CONDITIONS (Cont’d) Figure 59. High LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER RESET IN THIS AREA 8 0 2.5 Figure 60. Medium LVD Threshold Versus V f [MHz] OSC 16 DEVICE UNDER RESET IN THIS ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 15.4 SUPPLY CURRENT CHARACTERISTICS The following current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- Symbol Parameter ∆I ...
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SUPPLY CURRENT CHARACTERISTICS (Cont’d) 15.4.2 Wait and Slow Wait Modes Symbol Parameter Supply current in Wait mode (see Figure 64) Supply current in Slow Wait mode (see Figure 65 Supply current in Wait mode (see Figure 64) Supply ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto SUPPLY CURRENT CHARACTERISTICS (Cont’d) 15.4.3 Halt and Active Halt Modes Symbol Parameter Supply current in Halt mode I DD Supply current in Active Halt mode 15.4.4 Supply and Clock Managers The previous current consumption specified for the ...
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CLOCK AND TIMING CHARACTERISTICS Subject to general operating conditions for V 15.5.1 General Timings Symbol Parameter t Instruction cycle time c(INST) Interrupt reaction time t = ∆t v(IT v(IT) c(INST) 15.5.2 External Clock Source Symbol Parameter ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto CLOCK AND TIMING CHARACTERISTICS (Cont’d) 15.5.3 Crystal and Ceramic Resonator Oscillators The ST7 internal clock can be supplied with four different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with ...
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CLOCK AND TIMING CHARACTERISTICS (Cont’d) 15.5.3.2 Typical Ceramic Resonators Symbol t Ceramic resonator start-up time SU(osc) Note the typical oscillator start-up time measured between V SU(OSC) quick V ramp-up from (<50µs). DD Figure 68. Application ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto CLOCK AND TIMING CHARACTERISTICS (Cont’d) Table 23. Typical Ceramic Resonators f Option Byte OSC Config. (MHz) CSB1000JA 1 CSBF1000JA LP CSTS0200MGA06 2 CSTCC2.00MGA0H6 CSTS0200MGA06 2 CSTCC2.00MGA0H6 MP CSTS0400MGA06 4 CSTCC4.00MGA0H6 CSTS0400MGA06 4 CSTCC4.00MGA0H6 MS CSTS0800MGA06 8 CSTCC8.00MGA0H6 ...
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CLOCK CHARACTERISTICS (Cont’d) 15.5.4 RC Oscillators The ST7 internal clock can be supplied with an RC oscillator. This oscillator can be used with internal Symbol Parameter Internal RC oscillator frequency f OSC External RC oscillator frequency Internal RC Oscillator Start-up ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto CLOCK CHARACTERISTICS (Cont’d) 15.5.5 Clock Security System (CSS) Symbol Parameter f Safe Oscillator Frequency SFOSC f Glitch Filtered Frequency GFOSC Figure 72. Typical Safe Oscillator Frequencies fosc [kHz] -40°C 400 +25°C 350 300 250 200 3.2 VDD ...
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MEMORY CHARACTERISTICS 15.6.1 RAM and Hardware Registers Symbol Parameter V Data retention mode RM 15.6.2 EEPROM Data Memory Symbol Parameter t Programming time for 1~16 bytes prog 5) t Data retention ret 5) N Write erase cycles RW 15.6.3 ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 15.7 EMC CHARACTERISTICS Susceptibility tests are performed on a sample ba- sis during product characterization. 15.7.1 Functional EMS (Electromagnetic Susceptibility) Based on a simple running application on the product (toggling two LEDs through I/O ports), the product ...
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EMC CHARACTERISTICS (Cont’d) 15.7.2 Absolute Electrical Sensitivity Based on three different tests (ESD, LU and DLU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, re- fer ...
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... GENERATOR Notes: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the JEDEC criteria (international standard). 2. Schaffner NSG435 with a pointed test finger. ...
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EMC CHARACTERISTICS (Cont’d) 15.7.3 ESD Pin Protection Strategy To protect an integrated circuit against Electrostat- ic Discharge the stress must be controlled to pre- vent degradation or destruction of the circuit ele- ments. The stress generally affects the circuit ele- ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto EMC CHARACTERISTICS (Cont’d) True Open Drain Pin Protection The centralized protection (4) is not involved in the discharge of the ESD stresses applied to true open drain pads due to the fact that a P-Buffer and diode ...
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I/O PORT PIN CHARACTERISTICS 15.8.1 General Characteristics Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys I Input leakage current L ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto I/O PORT PIN CHARACTERISTICS (Cont’d) 15.8.2 Output Driving Current Subject to general operating conditions for V Symbol Parameter Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure ...
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I/O PORT PIN CHARACTERISTICS (Cont’d) Figure 86. Typical V vs Vol [V] at Iio=2mA Ta=-40°C 0.5 Ta=25°C 0.45 0.4 0.35 0.3 0.25 0.2 3.2 3.5 4 Vdd [V] Figure 87. Typical V vs Ta=-40°C ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 15.9 CONTROL PIN CHARACTERISTICS 15.9.1 Asynchronous RESET Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH V Schmitt trigger voltage hysteresis hys Output low ...
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CONTROL PIN CHARACTERISTICS (Cont’d) Figure 90. Typical I vs Ion [µA] Ta=-40°C 200 Ta=25°C 150 100 50 0 3.2 3.5 4 4.5 Vdd [V] Figure 92. Typical V vs Vol [V] at Iio=2mA 0.55 ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto CONTROL PIN CHARACTERISTICS (Cont’d) 15.9.2 ISPSEL Pin Subject to general operating conditions for V Symbol Parameter V Input low level voltage IL V Input high level voltage IH I Input leakage current L Figure 93. Two Typical ...
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TIMER PERIPHERAL CHARACTERISTICS Subject to general operating conditions for and T unless otherwise specified. OSC A 15.10.1 Watchdog Timer Symbol Parameter t Watchdog time-out duration w(WDG) 15.10.2 16-Bit Timer Symbol Parameter t Input capture pulse time ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 15.11 COMMUNICATION INTERFACE CHARACTERISTICS 15.11.1 SPI - Serial Peripheral Interface Subject to general operating conditions for and T unless otherwise specified. OSC A Symbol Parameter f SCK SPI clock frequency 1/t c(SCK) t r(SCK) ...
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COMMUNICATION INTERFACE CHARACTERISTICS (Cont’d) Figure 95. SPI Slave Timing Diagram with CPHA = 1 SS INPUT t su(SS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 t w(SCKH) t a(SO) t w(SCKL) see MISO OUTPUT HZ note 2 t su(SI) MOSI INPUT Figure 96. ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d) 15.11.2 SCI - Serial Communications Interface Subject to general operating condition for and T unless otherwise specified. OSC A Refer to I/O port characteristics for more details on the input/output ...
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ADC CHARACTERISTICS Subject to general operating conditions for V Symbol Parameter f ADC clock frequency ADC V Conversion range voltage AIN R External input resistor AIN C Internal sample and hold capacitor ADC t Stabilization time after ADC ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 8-BIT ADC CHARACTERISTICS (Cont’d) ADC Accuracy Symbol Parameter Total unadjusted error Offset error Gain Error Differential linearity error Integral linearity error ...
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PACKAGE CHARACTERISTICS 16.1 PACKAGE MECHANICAL DATA Figure 99. 64-Pin Thin Quad Flat Package (14x14 Figure 100. 44-Pin Thin Quad Flat Package (10x10 ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto A Dim ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto PACKAGE CHARACTERISTICS (Cont’d) 16.2 THERMAL CHARACTERISTICS Symbol Package thermal resistance (junction to ambient) R thJA P Power dissipation D Maximum junction temperature T Jmax Notes: 1. The power dissipation is obtained from the formula ...
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DEVICE CONFIGURATION AND ORDERING INFORMATION 17.1 INTRODUCTION Each device is available for production in user pro- grammable versions (Flash) as well as in factory coded versions (ROM). EEPROM data memory and Flash devices are shipped to customers with a ...
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... Code name (defined by STMicroelectronics -40 to +85° -40 to +105° -40 to +125° Plastic TQFP ST72334J2, ST72334J4, ST72334N2, ST72334N4, ST72314J2, ST72314J4, ST72314N2, ST72314N4, ST72124J2 A = -40 to +85° -40 to +125° Plastic TQFP ST72C334J2, ST72C334J4, ST72C334N2, ST72C334N4, ST72C314J2, ST72C314J4, ST72C314N2, ST72C314N4, ST72C124J2 ...
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... ST72P334N2T | Conditioning Tape and Reel Marking Standard marking Authorized characters are letters, digits, '.', '-', '/' and spaces only. Please consult your local STMicroelectronics sales office for other marking details if required. Temperature Range -40°C to +85°C Clock Source Selection: Resonator: RC Network: External Clock: ...
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... ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 17.4 DEVELOPMENT TOOLS STMicroelectronics offers a range of hardware and software development tools for the ST7 micro- controller family. Full details of tools available for the ST7 from third party manufacturers can be ob- tain from the STMicroelectronics Internet site www.st.com. Tools from these manufacturers include C compli- ers, emulators and gang programmers ...
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DEVELOPMENT TOOLS (Cont’d) 17.4.1 Suggested List of Socket Types Table 29. Suggested List of TQFP64 Socket Types Package / Probe ENPLAS TQFP64 YAMAICHI EMU PROBE YAMAICHI Table 30. Suggested List of TQFP44 Socket Types Package / Probe ENPLAS TQFP44 YAMAICHI ...
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ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto 18 IMPORTANT NOTES 18.1 SCI BAUD RATE REGISTERS Caution: The SCI baud rate register (SCIBRR) MUST NOT be written to (changed or refreshed) while the transmitter or the receiver is enabled. 148/150 ...
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... ST72124J2-Auto device - added operating temperature range specific to ROM devices Section 1 "PREAMBLE: ST72C334-Auto VERSUS ST72E331 SPECIFICATION" on page Replaced ST72C334 with ST72C334-Auto Section 2 "INTRODUCTION" on page Section 3 "PIN DESCRIPTION" on page Figure 3.44-Pin TQFP Package Pinout (J Table 1, “ ...
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... ST72334xx-Auto, ST72314xx-Auto, ST72124Jx-Auto Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...