AM79C874 Advanced Micro Devices, AM79C874 Datasheet
AM79C874
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AM79C874 Summary of contents
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... Idle wire: no wire signal, no receiver power Typical power = 285 mW; MAC saves over 100 mW GENERAL DESCRIPTION The Am79C874 NetPHY-1LP device provides the phys- ical (PHY) layer and transceiver functions for one 10/100 Mbps Ethernet port. It delivers the dual benefits of CMOS low power consumption and small package size ...
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... Framer Clock Recovery Carrier Detect Link Monitor Signal Detect Stream Cipher 4B/5B 25 MHz 10BASE-T Control/Status 20 MHz PLL Clk Generator Test LED Control XTL+ XTL- TEST LED CLK Drivers Am79C874 100TX TP_PMD MLT-3 TX+ BLW 100RX TX- Mux 10TX Transformer 10RX RX+ RX- RX FLP Auto- 25 MHz ...
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... Am79C874 51 NetPHY-1LP Am79C874 EQVCC ADPVCC LEDDPX/LEDTXB LEDSPD[1]/LEDTXA/CLK25EN ANEGA TECH_SEL[0] TECH_SEL[1] TECH_SEL[2] CRVVCC CRVGND OGND2 OVDD2 LEDLNK/LED_10LNK/LED_PCSBP_SD LEDTX/LEDBTB LEDRX/LEDSEL LEDCOL/SCRAM_EN LEDSPD[0]/LEDBTA/FX_SEL INTR CRS/10CRS COL/10COL 22235I-2 3 ...
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... DEVICE NUMBER/DESCRIPTION Am79C874 NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver Valid Combinations list configurations planned to be sup- VC ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and VI to check on newly released combinations. Am79C874 Valid Combinations ...
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... HomePHY™ Single-Chip 1/10 Mbps Home Networking PHY Physical Layer Devices (Multi-Port) Am79C875 NetPHY™-4LP Low Power Quad10/100-TX/FX Ethernet Transceiver Integrated Repeater/Hub Devices Am79C984A Enhanced Integrated Multiport Repeater (eIMR™) Am79C985 Enhanced Integrated Multiport Repeater Plus (eIMR+™ Am79C874 5 ...
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... Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 LED Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Power Savings Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Selectable Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Unplugged . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Idle Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 PHY CONTROL AND MANAGEMENT BLOCK (PCM BLOCK .28 Register Administration for 100BASE-X PHY Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Description of the Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Bad Management Frame Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Am79C874 ...
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... Figure 7.PHY Management Read and Write Operations Figure 8.MLT-3 Receive Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 9.MLT-3 and 10BASE-T Test Load with 1:1 Transformer Ratio Figure 10.MLT-3 and 10BASE-T Test Load with 1.25:1 Transformer Ratio . . . . . . . . . . . . . . . . . 44 Figure 11.Near-End 100BASE-TX Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 12.10BASE-T Waveform With 1:1 Transformer Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . Am79C874 7 ...
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... Table 20.Interrupt Control/Status Register (Register 17 .37 Table 21.Diagnostic Register (Register 18 .37 Table 22.Power/Loopback Register (Register 19 .38 Table 23.Mode Control Register (Register 21 .39 Table 24.Disconnect Counter (Register 23 .40 Table 25.Receive Error Counter Register (Register 24 . Am79C874 ...
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... CRVGND TX_ER/TXD[4] 52 CRVVCC TX_CLK/10TXCLK/ 53 TECH_SEL[2] PCSBP_CLK TX_EN/10TXEN 54 TECH_SEL[1] DGND2 55 TECH_SEL[0] VDD2 56 ANEGA LEDSPD[1]/ TXD[0]/10TXD 57 LEDTXA/CLK25EN TXD[1] 58 LEDDPX/LEDTXB TXD[2] 59 ADPVCC TXD[3] 60 EQVCC Am79C874 Pin No. Pin Name 61 RPTR 62 TEST3/SDI+ 63 RX- 64 RX+ 65 EQGND 66 TEST0/FXR- 67 TEST1/FXR+ 68 TEST2 69 FXT+ 70 FXT- 71 REFGND 72 IBREF 73 REFVCC 74 XTL- 75 XTL+ ...
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... When RX_ER is active high, it indicates an error has been detected during frame reception. This pin becomes the highest-order bit of the receive 5- bit code group in PCS bypass (PCSBP=HIGH) mode. This output is ignored in 10BASE-T operation. Am79C874 Output, High Impedance Output, High Impedance Output, High Impedance Output, High Impedance ...
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... MII Register 0, bit 10. In repeater mode, ISO will not tri-state the CRS pin. When this pin is left unconnected, the MII output pins are not in the high impedance state. Am79C874 Output, High Impedance Input, Pull-Down Input, Pull-Down Input, Pull-Down ...
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... MAC to access management registers within the Net- PHY-1LP device. This pin has an internal pull-down, therefore, it requires a 1 pull-up resistor as speci- fied in IEEE 802.3 when interfaced with a MAC. This pin can be left unconnected when management is not used. Am79C874 Input/Output, Pull-Up Input/Output, Pull-Down Pull-Down ...
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... Signal Detect. Refer to Table 4 and Figure 4 in the LED Port Configu- ration section if the device is operating in the standard LED mode. See Table 5 and Figure 5 if the device is op- erating in the advanced LED mode. Am79C874 Input Input/Output, Pull-Up Input/Output, Pull-Up Output ...
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... PLL (pins 10 and 11), Clock Re- covery (pins 51 and 52), Equalizer (pins 60 and 65), and Bandgap Reference (pins 71 and 73) areas. The other bypass capacitors should be placed as close to the pins as possible. Am79C874 Output Analog Power Power ...
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... TX_ER (transmit coding error) transi- tions synchronously with respect to TX_CLK. If TX_ER is asserted for one or more clock periods, and TX_EN is asserted, the PHY will emit one or more symbols that are not part of the valid data de- limiter set somewhere in the frame being transmit- ted. Am79C874 15 ...
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... MLT-3 data stream from the network. For 100BASE-TX, it then recovers the clock from the data stream, de-serializes the data stream, and descrambles/decodes the data stream (5B/4B) be- fore presenting it at the MII interface. Am79C874 7-Wire (GPSI) Not used Carrier Sense Detect ...
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... An energy detect circuit is also added to determine whether there is any signal energy on the media. This is useful in the power-saving mode. (See the description in Power Am79C874 HFBR/HFCT-5903 3.3 V MT-RJ 5 RD+ 4 RD- 3 SD+ ...
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... In 100BASE-FX mode, the external fiber-optic receiver performs the signal energy detection function and com- municates this information directly to the NetPHY-1LP device through the SDI+ pin. Am79C874 ...
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... Transmit Error; used to force signaling errors Am79C874 Interpretation Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 ...
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... This not only simplifies the system/circuit design, but also elim- inates any random/systematic offset on the receive path. In 10BASE-T and 100Base-FX modes, the base- line wander correction circuit is not required and there- fore will be bypassed. Am79C874 ...
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... Only one external 25 MHz crystal or a signal source is required as a reference clock. After power-on or reset, the PLL clock synthesizer is defaulted to generating the 20 MHz clock output and will stay active until the 100BASE-X operation mode is selected. Am79C874 RJ45 Connector (8) (7) TX+ (1) ...
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... TX± circuits are active for an excessive period (20-150 ms). This prevents one port from disrupting the network due to a stuck-on or faulty transmitter condi- tion. If the maximum transmit time is exceeded, the data path through the 10BASE-T transmitter circuitry is disabled (although Link Test pulses will continue to be Am79C874 ...
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... The NetPHY-1LP device can also check for a 10BASE-T NLP or 100BASE-TX idle symbol. If either is detected, the de- vice automatically configures to match the detected op- erating speed in half-duplex mode. This ability allows the device to communicate with legacy 10BASE-T and 100BASE-TX systems. Am79C874 23 ...
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... During remote loopback, signal detect (SD) output is forced to logic zero. Note that remote loopback operates only in 100BASE-TX mode. Am79C874 ANEG-EN Capabilities/ANEG No All Capabilities No ...
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... Am79C874 ) should be selected L LEDTX LEDRX LEDCOL ...
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... Table 5. Advanced LED Selections LEDTX/ LEDBTB LEDBT/ LEDTXA (Pin 47 Flash (Note means logic level low at the pin means logic level high at the pin. Am79C874 VCC 330 VCC 330 VCC 330 VCC 330 VCC 330 VCC 330 VCC 330 ...
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... RX_CLK will re- sume operation one clock period prior to the assertion of RX_DV. The receive clock will again shut off 64 clock cycles after RX_DV gets deasserted. Typical power savings of 100 mW can be realized in some MACs. Am79C874 300 Dual-Color LED 10BASE-T LED Indicator ...
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... Register Address TA MII Status, 1h Read Operation Register Address TA MII Control, 0h Write Operation Am79C874 TA DATA IDLE Z0 D...........D 10 D...........D DATA XXXXXXXXXPPAAAAA XXXXXXXXXPPAAAAA Register Data Idle z 0 ...
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... Serial Management Registers A detailed definition of each Serial Management regis- ter follows. The mode legend is shown in Table 9. Table 9. Legend for Register Table Type Description RW Readable and writable SC Self Clearing LL Latch Low until clear RO Read Only RC Cleared on the read operation LH Latch high until clear Am79C874 29 ...
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... TX_EN signal. Collision test is disabled if PCSBP 0 7 Collision Test pin is high. Collision test is enabled regardless of the duplex mode disable COL test. 0 6:0 Reserved Write as 0, ignore when read Am79C874 Read/ Write Default RW/ Set by RW TECH[2:0] pins ...
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... PHY Identifier 1 Register (Register 2) Table 12. PHY Identifier 1 Register (Register 2) Reg Name Description Composed of the 3rd through 18th bits of the Organizationally 2 15 OUI Unique Identifier (OUI), respectively Am79C874 Read/ Write Default RO 0 set by RO TECH[2:0] pins set by ...
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... Full Duplex Default is set by Register 1.12 Mbps Half Duplex. 10BASE Mbps Half Duplex capability Half Duplex Default is set by Register 1.11. 4 4:0 Selector Field [00001] = IEEE 802. Am79C874 Read/ Write Default RO 010101 RO 100001 RO 1011 Read/ Write Default RW 0 ...
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... No Link Partner Acknowledgement 1 = Link Partner message Page Request Link partner Message Page Request 1 = Link Partner can Comply Next Page Request 0 = Link Partner cannot Comply Next Page Request Link Partner Toggle Link Partner’s Message Code Am79C874 Read/ Write Default ...
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... Auto-Negotiation Link Partner Ability Register. This bit is cleared upon reading this register Link partner is auto-negotiation able. Link Partner Auto Negotiation Able 0 = Link partner is not auto-negotiation able Am79C874 Read/ Write Default RO 0 RO/ ...
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... CODE Message/Un-formatted Code Field. Reserved Registers (Registers 8-15, 20, 22, 25-31) The NetPHY-1LP device contains reserved registers at addresses 8-15, 20, 22, 25-31. These registers should be ignored when read and should not be written at any time Am79C874 Read/ Write Default ...
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... A 0 indicates that RX_CLK runs continuously during LINK whether data is received or not In loopback and PCS bypass modes, writing to this bit does not affect RX_CLK. Receive clock will be constantly active Am79C874 Read/ Write Default Set by RW ...
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... Receive PLL has locked onto received signal for selected data-rate (10BASE-T or 100BASE-X RX_LOCK 0 = Receive PLL has not locked onto received signal. This bit remains set until it is read. 18 7:0 Reserved Ignore when read Am79C874 Read/ Write Default ...
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... In Auto-Negotiation test mode, send NLP instead of FLP in NLP Link Integrity order to test NLP receive integrity Test 0 = Sending FLP in Auto-Negotiation test mode Reduce time constant for Auto-Negotiation timer Reduce Timer 0 = Normal operation Am79C874 Read/ Write Default ...
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... EN_SCRM 0 = Disable data scrambling. When FX mode is selected, this bit will be forced Bypass PCS PCSBP 0 = Enable PC mode selected FX_SEL 0 = Disable FX mode Am79C874 Read/ Write Default Set by ...
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... Count of PLL lock drop events counter Receive Error Counter Register (Register 24) Table 25. Receive Error Counter Register (Register 24) Reg Bit Name Description 24 15:0 RX_ER counter Count of receive error events Am79C874 Read/ Write Default RW 0000 Read/ Write Default RW 0000 ...
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... PECL Load V DD PECL Load V DD MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load V = Maximum DD VIN = 0 Maximum DD VIN = 2.7 V MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load MLT-3/10BASE-T Test Load Am79C874 ) . . . . . . . . . . . . . . +3.3 V ± +3.3 V ±5% DD Maximum Units 0.8 V 2.0 V 0.4 V 2.4 V 0.4 V –0.4 V – 1.5 V – ...
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... Sinusoid 5 MHz<f<10 MHz MLT-3/10BASE-T Test Load 0.4 V < VOUT < 10BASE-T, idle 10BASE-T, normal activity 10BASE-T, peak 100BASE-TX 100BASE-TX, no cable Power down MIN. SDA . XTL– limits up to 6.0 mA for I and –6.0 mA for Am79C874 Minimum Maximum Units 300 585 mV 150 293 mV - 2.2 2.8 mA ...
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... Will be Change Changing from from May Will be Change Changing from from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State Figure 8. MLT-3 Receive Input Am79C874 KS000010-PAL 22235I-10 43 ...
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... TX+ TX- Figure 10. MLT-3 and 10BASE-T Test Load with 1.25:1 Transformer Ratio Isolation 49.9 Transformer • 1:1 • 100 0.1 µ 0.01 µF Chassis Ground V DD Isolation 78.1 Transformer • 1:25:1 • 100 0.1 µ 0.01 µF Chassis Ground Am79C874 2% 22235I-11 2% 22235I-12 ...
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... TXOS +V TXOUT TX± -V TXOUT Figure 11. Near-End 100BASE-TX Waveform V TX10NE TX 10BASE-T 0 Figure 12. 10BASE-T Waveform With 1:1 Transformer Ratio 5V 82.5 Pin 130 Figure 13. PECL Test Loads Am79C874 V TXOUT 112 Pin 183 22235I-13 22235I-14 22235I-15 45 ...
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... TXR CLK CLKH CLKL CLF Figure 14. Clock Signal TXF XTDCD Figure 15. MLT-3 Test Waveform Am79C874 Min. Max. Unit 39.998 40.002 CLR 80% 22235I-16 20% Min ...
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... MDC MDIO Figure 16. Management Bus Transmit Timing MDC MDIO Figure 17. Management Bus Receive Timing MDPER t t MDWH MDWL t MDPD mdio_tx.vsd t t MDS MDH Am79C874 Min. Max. Unit 22235I-18 22235I-19 47 ...
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... MTS100 TX_EN CRS COL TX_ER TXD[3:0] TX± Figure 18. 100 Mbps MII Transmit Start of Packet Timing MTP100 t t MTWH100 MTWL100 t MTECRH100 t MTECOH100 t MTS100 t MTEJ100 Am79C874 Min. Max. Unit 140 200 ns - 160 ns 13 240 ...
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... Mbps MII Transmit Timing (Continued) TX_CLK TX_EN CRS COL TX± Figure 19. 100 Mbps Transmit End of Packet Timing MTIDLE100 t MTDCRL100 t MTDCOL100 /T/ Am79C874 /J/ 22235I-21 49 ...
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... RXD[3:0], RX_DV, RX_ER valid after the Rising Edge of RX_CLK MRCRD100 RX± /J/K/ t MRJCRH100 CRS t MRJCOH100 COL RX_CLK RXD[3:0] RX_DV RX_ER Figure 20. 100 Mbps MII Receive Start of Packet Timing MRJRA100 t MRRDC100 t MRCRD100 Am79C874 Min. Max. Unit - 200 ns 80 150 ns 130 240 ns 130 240 ns 120 140 ...
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... Mbps MII Receive Timing (Continued) /T/R/ RX± t MRTCRL100 CRS t MRTCOL100 COL RX_CLK RXD[3:0] RX_DV RX_ER Figure 21. 100 Mbps MII Receive End of Packet Timing MRERL100 Am79C874 22235I-23 51 ...
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... TX_CLK LOW MTWL10 t MTWH10 TX_CLK t MTS10 TX_EN TXD[3:0] t MTECRH10 CRS t MTECLH10 COL TX± Figure 22. 10 Mbps MII Transmit Start of Packet Timing MTP10 t MTWL10 t MTS10 t MTH100 t MTEP10 Am79C874 Min. Max. Unit 240 360 ns - 130 ns - 300 ns - ...
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... TX_CLK TX_EN t CRS t COL TX± Figure 23. 10 Mbps MII Transmit End of Packet Timing t MTIDLE10 MTDCRL10 MTDCOL10 Am79C874 22235I-25 53 ...
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... End of Packet to RXD[3:0], RX_DV, RX_ER De-Asserting (Going t MRERL10 LOW) RX± t MRPCRH10 CRS t MRPCOH10 COL RX_CLK t MRCHR10 RXD[3:0] RX_DV RX_ER Figure 24. 10 Mbps MII Receive Start of Packet Timing MRRC10 t MRCR10 Am79C874 Min. Max. Unit 80 150 ns 80 150 ns 100 100 ...
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... Mbps MII Receive Timing (Continued) RX± CRS COL RX_CLK RXD[3:0] RX_DV RX_ER Figure 25. 10 Mbps MII Receive End of Packet Timing MRECRL10 t MRECOL10 t MRERL10 Am79C874 22235I-27 55 ...
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... Bit Cell 2 Bit Cell 3 Bit Cell GRCD 1 0 Bit N t GRCD t GRCD Bit ( Bit N Am79C874 Min. Max. 750 850 45 55 Bit Cell GRCD t GCD 22235I-28 Min. Max ...
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... Collision End to 10COL LOW GCECLL Collision 0 V Presence± 10COL Bit N t GDOFF Bit ( Bit GCSCLH Figure 29. GPSI Collision Timing Am79C874 Min. Max. 190 GRCD 22235I-30 Min. Max. 80 150 125 185 t GCECLL ...
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... Figure 31. GPSI Transmit 10TXCLK and 10TXD Timing Figure 32. Test Load for 10RXD, 10CRS, 10RXCLK, 10TXCLK and 10COL GTTX t GTCP t GTCH t GTCL t GTCDH t GDTCS DUT 50 pF Am79C874 Min. Max. Unit 240 360 ns 22235I-32 Min. Max. Unit 20 ...
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... PHYSICAL DIMENSIONS PQT80 (measured in millimeters Am79C874 Dwg rev. AE; 8/99 PQT80 59 ...
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... AMD, the AMD logo and combinations thereof, PCnet-PRO and NetPHY are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies and V OHL , Figure 6, Advanced LED Configuration, changes to Re OZ. Am79C874 ...