ISPLSI1048-80LQ Lattice Semiconductor Corp., ISPLSI1048-80LQ Datasheet
ISPLSI1048-80LQ
Specifications of ISPLSI1048-80LQ
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ISPLSI1048-80LQ Summary of contents
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... Tools, Timing Simulator and ispANALYZER™ — PC and UNIX Platforms Copyright © 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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Functional Block Diagram Figure 1. ispLSI 1048 Functional Block Diagram I/O I/O I/O I RESET Generic Output Routing Pool (ORP) Logic Blocks (GLBs I I I/O 3 I/O ...
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Absolute Maximum Ratings Supply Voltage V .................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150 C Case Temp. with Power Applied .............. -55 ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure 2) Test Condition R1 A ...
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External Timing Parameters 5 2 TEST PARAMETER # DESCRIPTION COND. t pd1 A 1 Data Propagation Delay, 4PT bypass, ORP bypass Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Inputs t iobp 20 I/O Register Bypass t iolat 21 I/O Latch Delay t iosu 22 I/O Register Setup Time before Clock t ioh 23 I/O Register Hold Time after Clock t ioco ...
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Internal Timing Parameters 2 PARAMETER DESCRIPTION # Outputs t ob Output Buffer Delay 47 t oen 48 I/O Cell OE to Output Enabled t odis 49 I/O Cell OE to Output Disabled Clocks t gy0 50 Clock Delay ...
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Timing Model I/O Cell Ded. In #26 I/O Reg Bypass I/O Pin #20 (Input) Input Register D Q RST #55 # 30, 31, 32 Reset Y1,2 Derivations of su, h and co ...
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Maximum GRP Delay vs GLB Loads Power Consumption Power consumption in the ispLSI 1048 device depends on two primary factors: the speed at which the device is operating, and the ...
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Pin Description NAME PQFP PIN NUMBERS I I/O 5 20, 21, 22, 23, 24, 25, I I/O 11 26, 27, 28, 29, 30, 31, I I/O 17 32, 33, 34, 35, 36, 37, I/O ...
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Pin Configuration ispLSI 1048 120-Pin PQFP Pinout Diagram I/O 94 ...
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Part Number Description ispLSI Device Family Device Number Speed MHz max MHz max MHz max ispLSI 1048 Ordering Information f Family max (MHz) 80 ispLSI ...