ISPLSI 1032E-70LTI LATTICE SEMICONDUCTOR, ISPLSI 1032E-70LTI Datasheet
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ISPLSI 1032E-70LTI
Specifications of ISPLSI 1032E-70LTI
Related parts for ISPLSI 1032E-70LTI
ISPLSI 1032E-70LTI Summary of contents
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... The basic unit of logic on the ispLSI 1032E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 1032E device ...
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... GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 1032E device are selected using the Clock Distribution Network. Four dedicated clock pins (Y0, Y1, Y2 and Y3) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells ...
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... IH o Capacitance (T =25 C, f=1.0 MHz) A SYMBOL PARAMETER C Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance 1 (Commercial/Industrial Clock Capacitance 2 Data Retention Specifications PARAMETER Data Retention Erase/Reprogram Cycles Specifications ispLSI 1032E 1 +1.0V CC +1.0V CC PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A TYPICAL MINIMUM 20 10000 3 MIN ...
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... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1032E Figure 2. Test Load GND to 3.0V -125 ≤ Others ≤ ...
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... Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Specifications ispLSI 1032E Over Recommended Operating Conditions 1 DESCRIPTION ...
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... Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. 2. Refer to Timing Model in this data sheet for further details. 3. Standard 16-bit counter using GRP feedback. 4. Reference Switching Test Conditions section. Specifications ispLSI 1032E Over Recommended Operating Conditions 1 DESCRIPTION ...
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... ORP Bypass Delay orpbp 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1032E 1 DESCRIPTION 3 7 -125 -100 UNITS MIN ...
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... ORP Delay orp t orpbp 48 ORP Bypass Delay 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 1032E -80 -70 -90 MIN. MAX. ...
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... Clk Delay, Clk GLB to I/O Cell Global Clk Line iocp Global Reset t 59 Global Reset to GLB and I/O Registers gr 1. Internal Timing Parameters are not tested and are for reference only. Specifications ispLSI 1032E 1 DESCRIPTION 9 -125 -100 UNITS MIN. MAX. ...
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... Clock Delay I/O Cell Global Clock Line t 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line iocp Global Reset Global Reset to GLB and I/O Registers 1. Internal Timing Parameters are not tested and are for reference only. Specifications ispLSI 1032E 1 DESCRIPTION 10 -80 -70 -90 MIN. MAX. MIN. ...
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... Clock (max) + Reg co + Output gy0(max) + gco + = (#54 + #42 + #56) + (#42) + (#47 + #49) 5 (1.4 + 2.3 + 1.8) + (2.3) + (1.0 + 1.3) 1. Calculations are based upon timing specifications for the ispLSI 1032E-125. Specifications ispLSI 1032E GRP GLB Feedback #34 Comb 4 PT Bypass GRP4 Reg 4 PT Bypass GLB Reg Bypass #30 #35 ...
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... I can be estimated for the ispLSI 1032E using the following equation (mA PTs * 0.59 nets * Max freq * 0.0078) CC Where PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The I estimate is based on typical conditions ( ...
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... NC pins are not to be connected to any active signals, Vcc or GND. 2. Pins have dual function capability. 3. Pins have dual function capability which is software selectable. Specifications ispLSI 1032E TQFP PIN NUMBERS Input/Output Pins - These are the general purpose I/O pins used by the logic ...
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... Pin Configurations ispLSI 1032E 84-Pin PLCC Pinout Diagram VCC 21 GND 22 ispEN 23 RESET 24 1 SDI Pins have dual function capability. 3. Pins have dual function capability which is software selectable. Specifications ispLSI 1032E ispLSI 1032E Top View 14 74 ...
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... Pin Configurations ispLSI 1032E 100-Pin TQFP Pinout Diagram VCC 12 GND 13 ispEN 14 RESET 15 1 SDI/ I Pins have dual function capability. 2. Pins have dual function capability which is software selectable pins are not to be connected to any active signal, VCC or GND. ...
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... INDUSTRIAL ORDERING NUMBER 15 ispLSI 1032E-70LJI 15 ispLSI 1032E-70LTI 16 X Grade Blank = Commercial I = Industrial Package J = PLCC T = TQFP JN = Lead-Free PLCC TN = Lead-Free TQFP Power L = Low PACKAGE 84-Pin PLCC 100-Pin TQFP 84-Pin PLCC ...
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... Ordering Information (Cont.) Lead-Free Packaging FAMILY fmax (MHz) tpd (ns) 125 125 100 ispLSI 100 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com. FAMILY fmax (MHz) tpd (ns) 70 ispLSI 70 1. 84-PLCC lead-free package is MSL4. Refer to "Handling Moisture Sensitive Packages" document on www.latticesemi.com. ...