MT90210AL Mitel, MT90210AL Datasheet
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MT90210AL
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MT90210AL Summary of contents
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... Boundary S23 Scan Test Multi-Rate Parallel Access Circuit DS5026 MT90210AL Description The MT90210 is a 100-pin device used to interface a parallel bidirectional 8 bit bus to 24 time division multiplexed (TDM) serial streams. The device is configured to perform simultaneous parallel-to-serial and serial-to-parallel conversion with the capability ...
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MT90210 VSS VDD 86 A10 VSS 88 A11 A12 90 RBC VDD 92 VSS WBC VSS 98 VDD S3 100 2 4 Note: the PQFP package ...
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Preliminary Information Pin Description (continued) Pin Name 31 SCLK Serial Port Clock (input). The SCLK clock is used to control the serial port operation in modes 1,2,3 and 4. Depending on the operation mode selected at the MD0-MD2 inputs, this ...
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MT90210 Pin Description (continued) Pin Name 58-59, P0-P1, Parallel Input/Output Data Bus. This 8 bit data bus is a bidirectional parallel port used to 61-62, P2-P3, perform 8-bit transactions between the MT90210 and the external dual port RAM. Data is ...
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Preliminary Information Functional Description The MT90210 is a 100-pin device that converts incoming serial telecom streams of 2.048, 4.096 or 8.192 Mb 8-bit parallel bus, and converts input data on this parallel bus to the outgoing serial ...
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MT90210 how the data from the serial port is mapped into the external dual port memory. 768 bytes for TX BLOCK 0 768 bytes for RX 768 bytes for TX BLOCK 1 768 bytes for RX MODE 1 24 bidirectional ...
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Preliminary Information 512 bytes for S0-S15 TX 1024 bytes for S16-S23 TX BLOCK 0 512 bytes for S0-S15 RX 1024 bytes for S16-S23 RX 512 bytes for S0-S15 TX 1024 bytes for S16-S23 TX BLOCK 1 512 bytes for S0-S15 ...
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MT90210 SCLK (4 MHz) SCLK (8 MHz) SCLK, C16 (16 MHz) F0i Serial I/O Ch. 31, Bit 1 2 Mb/s Serial I/O Ch. 63, Bit 2 Ch. 63, Bit 1 4 Mb/s Serial I/O Ch. 127, Ch. 127, Ch. 127, ...
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Preliminary Information RBC WBC 125 us Exclusive access of Block 0 Figure 7b - WBC and RBC operation in relation to accessing data from Block 0 and Block 1 SCLK PCLK A A0-A12 RD R/W1 R/W2 Strobe P0-P7 RD Note: ...
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MT90210 I[0:1] Instruction [00] EXTEST Boundary-Scan register selected, Test Enabled [01], SAMPLE/ Boundary-Scan [10] PRELOAD register selected, Test Disabled [11] BYPASS/ Bypass register NOTEST selected, Test Disabled Instruction Register In accordance with the IEEE 1149.1 standard, the MT90210 uses public ...
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Preliminary Information ST-BUS SCSA 24 S0-S23 MVIP H-MVIP Mode 1: 4.096 MHz Mode 2: 8.192 MHz Mode 3 & 4: 16.384 MHz SCLK 8 kHz F0i Mode 5: 16.384 MHz C16+ Mode 5: 16.384 MHz C16- Mode 4 & 5: ...
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MT90210 PLLAGND LP1 LP2 R1= 3k R2= 100 + 5% C1= 10nF + 5% C2= 20pF Figure 10 - Analog PLL Low Pass Filter Circuit PLL Considerations The MT90210 device contains an analog Phase- Locked Loop (PLL) which is used ...
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Preliminary Information PCLK Cycle Read ...
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MT90210 PCLK Cycle Read Write ...
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Preliminary Information F0i S23:S0 Frame n, last channel P7:P0 Write data from S23-S0 frame last channel Finished reading last channel of frame n RBC WBC R/W1 R/W2 STROBE Figure 12 - Modes Read/Write Timing ...
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MT90210 2M ts Frame n, channel 124 ch 125 3 channel delay for 8 Mb/s rate P7:P0 Finished reading last channel of 8Mb/s th and 4 quarter of last channel of 2 Mb/s of one complete ...
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Preliminary Information Absolute Maximum Ratings Parameter 1 DC Power Supply Voltage Voltage on any pin (other than supply pins) 3 Current at any pin (except Package Power Dissipation *Exceeding these values may cause permanent ...
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MT90210 AC Electrical Characteristics timing specifications. The setup/hold and propagation delays are based on a single reference level which is 1.5V for TTL(V CMOS ( Voltage Value when Voltage Reference Connected to TTL ...
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Preliminary Information clock drive to drive output drive to hiz-low output drive to hiz-high output F0i SCLK 4.096 MHz (Mode 1) 8.192 MHz (Mode 2) 16.384 MHz (Mode 3) S0-23 bit 0, last ch (inputs) S0-23 bit 0, last ch ...
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MT90210 F0i (8kHz) S0-15 bit 0, ch. 31 (2.048 Mb/s) (inputs) S0-15 bit 0, ch. 31 (2.048 Mb/s) (outputs) t HC4 hclkl (4.096 MHz) t clkl (16.384 MHz) t clkh t clk S16-S23 (8.192 Mb/s) (inputs) S16-S23 bit 1, ch. ...
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Preliminary Information AC Electrical Characteristics Characteristics 1 SCLK, C16 Period 2.048 Mb/s (4.096 MHz) 4.096 Mb/s (8.192 MHz) 8.192 Mb/s (16.384 MHz) 2 SCLK, C16 Pulse Width High 2.048 Mb/s 4.096 Mb/s 8.192 Mb/s 3 SCLK, C16 Pulse Width Low ...
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MT90210 CKout (mode 3/4/5) t dpll SCLK C16+ C16 - SCLK or C16+, C16- CKout (16.384 MHz, mode 1) (32.768 MHz, mode 2/3/4/ A0-A12 X RDin input t st P0-P7 (Read/ X(rd) Write) Strobe t oes Valid OEser ...
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Preliminary Information SCLK or C16+, C16 - CKout (16.384 MHz, mode 1) (32.768 MHz, mode 2/3/4/ A0-A12 dod P0-P7 (Read/ WR(x) Write) t stb Strobe Note: R/W2 output signal is HIGH during ...
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MT90210 2-168 Preliminary Information ...
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Index Pin 1 44-Pin Dim Min Max A - 0.096 (2.45) A1 0.01 - (0.25) A2 0.077 0.083 (1.95) (2.10) b 0.01 0.018 (0.30) (0.45) D 0.547 BSC (13.90 BSC) D 0.394 BSC ...
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Package Outlines 160-Pin Dim Min 0.125 (3.17) b 0.009 (0.22) D 1.23 BSC (31.2 BSC) D 1.102 BSC 1 (28.00 BSC) E 1.23 BSC (31.2 BSC) E 1.102 BSC 1 (28.00 BSC) e 0.025 BSC (0.65 ...
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... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...