GS9060 Gennum Corporation, GS9060 Datasheet
GS9060
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GS9060 Summary of contents
Page 1
... This cable driver also features an output mute on loss of signal, high impedance mode, adjustable signal swing. The GS9060 also includes a range of data processing functions such as error detection and correction, automatic standards detection, and EDH support. The device can also detect and extract SMTPTE 352M payload identifier packets and independently identify the received video standard ...
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... Word alignment and flywheel S->P K28.5 sync detect, DVB-ASI word alignment and 8b/10b decode HOST Interface / JTAG Reset test GS9060 Functional Block Diagram 22208 - 8 January 2007 GS9060 Data Sheet DATA_ERROR DOUT[19:0] TRS correct TRS check CSUM correct CSUM check EDH check & I/O ...
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... Serial-To-Parallel Conversion .......................................................................28 3.6 Lock Detect ...................................................................................................28 3.6.1 Input Control Signals ..........................................................................29 3.7 SMPTE Functionality ....................................................................................30 3.7.1 SMPTE Descrambling and Word Alignment .......................................30 3.7.2 Internal Flywheel.................................................................................30 3.7.3 Switch Line Lock Handling..................................................................31 3.7.4 HVF Timing Signal Generation ...........................................................33 3.8 DVB-ASI Functionality ..................................................................................34 3.8.1 Transport Packet Format ....................................................................35 3.8.2 DVB-ASI 8b/10b Decoding and Word Alignment................................35 22208 - 8 January 2007 GS9060 Data Sheet ...
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... Device Reset...............................................................................................55 4. Application Reference Design ................................................................................56 4.1 Typical Application Circuit (Part A) ...............................................................56 4.2 Typical Application Circuit (Part B) ...............................................................57 5. References & Relevant Standards .........................................................................58 6. Package & Ordering Information............................................................................59 6.1 Package Dimensions ....................................................................................59 6.2 Packaging Data.............................................................................................60 6.3 Ordering Information .....................................................................................60 7. Revision History .....................................................................................................61 22208 - 8 January 2007 GS9060 Data Sheet ...
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... 22208 - 8 January 2007 GS9060 Data Sheet DATA_ERROR SDO ...
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... Used to select the output data bus width in SMPTE or Data-Through modes. This signal is ignored in DVB-ASI mode. When set HIGH, the parallel output will be 20-bit demultiplexed data. When set LOW, the parallel outputs will be 10-bit multiplexed data. 22208 - 8 January 2007 GS9060 Data Sheet ...
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... Input Used to set the serial digital loop-through output signal amplitude. Connect to CD_VDD through 281Ω +/- 1% for 800mV – Power Power supply connection for the serial digital cable driver. Connect to +1.8V DC analog. 22208 - 8 January 2007 GS9060 Data Sheet single-ended output swing. p ...
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... CS_TMS operates as the host interface chip select, CS, and is active LOW. JTAG Test Mode (JTAG/HOST = HIGH) CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH. NOTE: If the host interface is not being used, tie this pin HIGH. 22208 - 8 January 2007 GS9060 Data Sheet ...
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... ERROR_MASK register HIGH. All error conditions are detected by default. Synchronous Output CONTROL SIGNAL OUTPUT with PCLK Signal levels are LVCMOS/LVTTL compatible. Used as a control signal for external FIFO(s). Normally HIGH but will go LOW for one PCLK period at SAV. 22208 - 8 January 2007 GS9060 Data Sheet ...
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... PCLK Signal levels are LVCMOS/LVTTL compatible. DOUT9 is the MSB and DOUT0 is the LSB. 20-bit mode 20bit/10bit = HIGH 10-bit mode 20bit/10bit = LOW 22208 - 8 January 2007 GS9060 Data Sheet ) Chroma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data output in Data-Through mode ...
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... For 10-bit multiplexed data (20bit/10bit = LOW), the CANC signal will be HIGH when VANC or HANC data is detected anywhere in the data stream and LOW otherwise. 22208 - 8 January 2007 GS9060 Data Sheet Luma data output in SMPTE mode SMPTE_BYPASS = HIGH DVB_ASI = LOW Data output in Data-Through mode ...
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... Ground reference for the external voltage controlled oscillator. Connect to pins and 8 of the GO1555/GO1525*. This pin is an output. Should be isolated from all other grounds. *For new designs use GO1555 22208 - 8 January 2007 GS9060 Data Sheet PCLK = 13.5MHz PCLK = 27MHz ...
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... PLL lock time constant capacitor connection. Normally connected to VCO_GND through 2.2nF. Analog Input Control voltage to set the loop bandwidth of the integrated reclocker. Normally connected to VCO_GND through 40kΩ. – Power Ground connection for the charge pump. Connect to analog GND. 22208 - 8 January 2007 GS9060 Data Sheet ...
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... MIL STD 883 ESD protection applied to all pins on the device. Conditions Min – – – – – – – – – – – 22208 - 8 January 2007 GS9060 Data Sheet Value/Units -0.3V to +2.1V -0.3V to +4.6V -2. 5.25V -20°C < T < 85°C A -40°C < T < 125°C STG 230°C 1kV 18) Typ Max ...
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... RSET=281Ω 75Ω load, RSET=281Ω NOTES 1. All DC and AC electrical parameters within specification. 2. Input common mode is set by internal biasing resistors. 3. Set by the value of the RSET resistor. 4. Loop-through enabled. 22208 - 8 January 2007 GS9060 Data Sheet Typ Max Units – – 0.8 V 2.1 – ...
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... Load = 75Ω ORL compensation using recommended circuit ORL compensation using recommended circuit Pseudorandom and pathological – SDO – – – – – 22208 - 8 January 2007 GS9060 Data Sheet Typ Max Units 0.6 – – UI – – 197 us – – – 21 – ...
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... NOTES 1. 6MHz sine wave modulation 525i 3. Serial Digital Output Reclocked (RC_BYP = HIGH). 4. Serial Duty Cycle Distortion is defined here to be the 5. With 15pF load. 6. See 22208 - 8 January 2007 GS9060 Data Sheet Typ Max Units – – 6.6 MHz – ...
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... Figure 2-2: Maximum Pb-free Solder Reflow Profile (Pb-free package) 22208 - 8 January 2007 GS9060 Data Sheet Figure 2-1. MSL qualification was performed Figure 2-2. 60-150 sec. 10-20 sec. 3˚C/sec max 120 sec. max 6 min ...
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... Input/Output Circuits All resistors in ohms, all capacitors in farads, unless otherwise shown. DDI VDD 50 45K TERM 150K 50 DDI Figure 2-3: Serial Digital Input VCO VDD 25 1. VCO Figure 2-4: VCO Input 7.2K 865mV Figure 2-5: PLL Loop Bandwidth Control 22208 - 8 January 2007 GS9060 Data Sheet LB_CONT ...
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... Figure 2-6: Serial Digital Output LF CP_CAP 300 Figure 2-7: VCO Control Output & PLL Lock Time Capacitor 22208 - 8 January 2007 GS9060 Data Sheet SDO SDO ...
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... A 2x1 input multiplexer is provided to allow the application layer to select between the two serial digital input streams using a single external pin. When IP_SEL is set HIGH, serial digital input 1 (DDI1 / DDI1) is selected as the input to the GS9060's reclocker stage. When IP_SEL is set LOW, serial digital input 2 (DDI2 / DDI2) is selected ...
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... When LOW, CDx indicates that a valid serial digital data stream is being delivered to the GS9060 by the equalizer. When HIGH, the serial digital input to the device should be considered invalid equalizer precedes the device, the application layer should set CD1 and CD2 accordingly. ...
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... The internal regulator uses +3.3V DC supplied via the CP_VDD / CP_GND pins to provide +2. the VCO_VCC / VCO_GND pins. The control voltage to the VCO is output from the GS9060 on the LF pin and requires 4.7kΩ pull-up and pull-down resistors to ensure correct operation. The GO1555/GO1525* produces a reference signal for the reclocker, input on the VCO pin of the GS9060 ...
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... HIGH. If RC_BYP is set LOW, the data stream will bypass the internal reclocker and the serial digital output will be a buffered version of the input. The GS9060 will automatically mute the serial digital loop-through output when the internal carrier_detect signal indicates an invalid serial input. ...
Page 28
... HIGH if (1) the reclocker has locked to the input data stream as indicated by the internal pll_lock signal, and (2) TRS or DVB-ASI sync words have been correctly identified. 22208 - 8 January 2007 GS9060 Data Sheet 25, this signal will be LOW when a good serial 51. Table 2- ...
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... LOCKED signal will be asserted HIGH if and only if the SMPTE_BYPASS and DVB_ASI input pins are set LOW. The GS9060 contains three input control signals which determine how the device locks to the input required that the application layer set the SMPTE_BYPASS and DVB_ASI inputs to reflect the appropriate input data format ...
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... SMPTE Functionality 3.7.1 SMPTE Descrambling and Word Alignment 3.7.2 Internal Flywheel The GS9060 is said SMPTE mode once the device has detected SMPTE TRS sync words and locked to the input data stream as described in on page 28. The device will remain in SMPTE mode until such time that SMPTE TRS sync words fail to be detected ...
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... To account for the horizontal disturbance caused by a synchronous switch necessary to re-synchronize the flywheel immediately after the switch has taken place. Rapid re-synchronization of the GS9060 to the new video standard can be achieved by controlling the flywheel using the FW_EN/DIS pin. At every PCLK cycle the device samples the FW_EN/DIS pin. When a logic LOW to HIGH transition at this pin is detected anywhere within the active line, the flywheel will re-synchronize immediately to the next TRS word ...
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... The GS9060 also implements automatic switch line lock handling. By utilizing the synchronous switch points defined by SMPTE RP168 for all major video standards with the automatic video standards detect function, the device automatically re-synchronizes the flywheel at the switch point ...
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... BT.799 4:2:2 BT.601 The GS9060 extracts critical timing parameters from either the received TRS signals (FW_EN/DIS = LOW), or from the internal flywheel-timing generator (FW_EN/DIS = HIGH). Horizontal blanking period (H), vertical blanking period (V), and even / odd field (F) timing are all extracted and presented to the application layer via the H:V:F status output pins ...
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... H:V:F TIMING – 10-BIT OUTPUT MODE Figure 3- Timing The GS9060 conforms to DVB-ASI standard EN 50083-9:1998. The GS9060 is said DVB-ASI mode once the device has detected 32 consecutive DVB-ASI words without a single word or disparity error being generated. The device will remain in DVB-ASI mode until 32 consecutive DVB-ASI word or disparity errors are detected, or until SMPTE TRS ID words have been detected ...
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... Parallel DVB-ASI data may then be clocked out of the FIFO at some rate less than 27MHz. See Figure 3-4. WORDERR will be high whenever the device has detected an illegal code word. GS9060 Figure 3-4: DVB-ASI FIFO Implementation using the GS9060 22208 - 8 January 2007 GS9060 Data Sheet AOUT ~ HOUT 8 ...
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... Data Through Mode 3.10 Additional Processing Functions 3.10.1 FIFO Load Pulse The GS9060 may be configured by the application layer to operate as a simple serial-to-parallel converter. In this mode, the device presents data to the output data bus without performing any decoding, descrambling or word-alignment. Data through mode is enabled only when the SMPTE_BYPASS and DVB_ASI input pins are set LOW ...
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... YANC/CANC 3.10.2.1 Programmable Ancillary Data Detection The GS9060 will detect all types of ancillary data in either the vertical or horizontal blanking spaces and indicate via the status signal output pins YANC and CANC the position of ancillary data in the output data stream. These status signal outputs are synchronous with PCLK and can be used as clock enables to external logic write enables to an external FIFO or other memory device ...
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... SDID is set to zero, the device will detect all ancillary data types matching the DID value, regardless of the SDID. In the case where all five DID and SDID values are set to zero, the GS9060 will detect all ancillary data types. This is the default setting after device reset. ...
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... Automatic Video Standard and Data Format Detection The GS9060 can receive and detect the presence of the SMPTE 352M payload identifier ancillary data packet. This four word payload identifier packet may be used to indicate the transport mechanism, frame rate and line scanning / sampling structure ...
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... Data Format (see Name Not Used RASTER_STRUCTURE1[11:0] Not Used RASTER_STRUCTURE2[11:0] Not Used RASTER_STRUCTURE3[10:0] Not Used RASTER_STRUCTURE4[10:0] 22208 - 8 January 2007 GS9060 Data Sheet Table 3-8) Table 3-9). Description Words Per Active Line. Words Per Total Line. Total Lines Per Frame. Active Lines Per Field. R/W Default ...
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... SDTI CP 4h Other SDTI fixed block size 5h Other SDTI variable block size 6h SDI 7h DVB-ASI Reserved Fh Unknown data format 22208 - 8 January 2007 GS9060 Data Sheet Length Of Total SMPTE352M Active Video Samples 1440 1716 1440 1716 – 1716 – 1716 1440 1728 – ...
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... Error Detection and Indication The GS9060 contains a number of error detection functions to enhance operation of the device when operating in SMPTE mode. These functions, (except lock error detection), will not be available in either DVB-ASI or Data-Through operating modes. See Section 3.8 on page 34 The device maintains an error status register at address 01 ...
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... Full Field CRC Error Flag Mask bit. Active Picture CRC Error Flag Mask bit. Lock Error Flag Mask bit. Checksum Error Flag Mask bit. Start of Active Video Error Flag Mask bit. End of Active Video Error Flag Mask bit. 22208 - 8 January 2007 GS9060 Data Sheet R/W Default ...
Page 44
... EDH CRC Error Detection If a mismatch between the received SMPTE 352M packets and the calculated video standard occurs, the GS9060 will indicate a video standard error by setting the VD_STD_ERR bit of the ERROR_STATUS register HIGH. The GS9060 calculates Full Field (FF) and Active Picture (AP) CRC words according to SMPTE RP165 in support of Error Detection and Handling packets in SD signals ...
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... Field 1 Full Field end line data used to set EDH calculation range outside of SMPTE RP 165 values. The LOCKED pin of the GS9060 indicates the lock status of the reclocker and lock detect blocks of the device. Only when the LOCKED pin is asserted HIGH has the device correctly locked to the received data stream, The GS9060 will also indicate lock error to the host interface when LOCKED = LOW by setting the LOCK_ERR bit in the ERROR_STATUS register HIGH ...
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... If the ILLEGAL_REMAP bit of the IOPROC_DISABLE register is set LOW, the GS9060 will remap all codes within the active picture between the values of 3FCh and 3FFh to 3FBh. All codes within the active picture area between the values of 000h and 003h will be re-mapped to 004h. ...
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... Timing Reference Signal Insertion. Set HIGH to disable. The IOPROC_EN/DIS pin must be set HIGH. The GS9060 will generate and insert active picture and full field CRC words into the EDH data packets received by the device. This feature is only available in SD mode and is enabled by setting the EDH_CRC_INS bit of the IOPROC_DISABLE register LOW ...
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... EDH flags may be set, and the source is replaced by one without EDH packets, the EDH_FLAG register will not be cleared. NOTE 3: The GS9060 will detect EDH flags, but will not update the flags if an EDH CRC error is detected. Gennum's GS9062 Serializer allows the host to individually set EDH flags ...
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... SMPTE_BYPASS and DVB_ASI pins. Recall that these pins are set by the application layer as inputs to the device. The parallel data outputs of the GS9060 are driven by high-impedance buffers which support both LVTTL and LVCMOS levels. These buffers use a separate power supply of +3.3V DC supplied via the IO_VDD and IO_GND pins. ...
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... In addition, DOUT19 and DOUT18 will be configured as the DVB-ASI status signals SYNCOUT and WORDERR respectively. See a description of these DVB-ASI specific output signals. DOUT[9:0] will be forced LOW when the GS9060 is operating in DVB-ASI mode. When operating in Data-Through mode, presents data to the output data bus without performing any decoding, descrambling or word-alignment ...
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... Figure 3-8. All read or write access to the GS9060 is initiated and terminated by the host processor. Each access always begins with a 16-bit command word on SDIN indicating the address of the register of interest. This is followed by a 16-bit data word on SDIN in write mode 16-bit data word on SDOUT in read mode. ...
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... The command word is transmitted MSB first and contains a read/write bit, nine reserved bits and a 6-bit register address. Set R/W = '1' to read and R/W = '0' to write from the GSPI. Command words are clocked into the GS9060 on the rising edge of the serial clock SCLK. The appropriate chip select, CS, signal must be asserted low a minimum of 1.5ns (t ...
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... D14 Figure 3-12: GSPI Write Mode Timing Table 3-16 summarizes the GS9060's internal status and configuration registers. All of these registers are available to the host via the GSPI and are all individually addressable. Where status registers contain less than the full 16 bits of information however, two or more registers may be combined at a single logical address ...
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... JTAG When the JTAG/HOST input pin of the GS9060 is set HIGH, the host interface port will be configured for JTAG test operation. In this mode, pins 27 through 30 become TMS, TDO, TDI, and TCK. In addition, the RESET_TRST pin will operate as the test reset pin. Boundary scan testing using the JTAG interface will be enabled in this mode. ...
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... CORE_VDD RESET_TRST Because the GS9060 is designed to operate in a multi-volt environment, any power up sequence is allowed. The charge pump, phase detector, core logic, serial digital input/output buffers and digital I/O buffers should all be powered up within 1ms of one another. Device pins may also be driven prior to power up without causing damage. ...
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... 22208 - 8 January 2007 GS9060 Data Sheet 10n 1 16 CLI ...
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... 22208 - 8 January 2007 GS9060 Data Sheet ...
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... SMPTE 352M Video Payload Identification for Digital Television Interfaces SMPTE RP165 Error Detection Checkwords and Status Flags for Use in Bit-Serial Digital Interfaces for Television SMPTE RP168 Definition of Vertical Interval Switching Point for Synchronous Video Switching 22208 - 8 January 2007 GS9060 Data Sheet ...
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... Package & Ordering Information 6.1 Package Dimensions 22208 - 8 January 2007 GS9060 Data Sheet Table X CONTROL DIMENSIONS ARE IN MILLIMETERS. Table Y SY MBO L MILLI METER MIN N OM MAX b 0.22 0. 009 0. 012 0 . 015 12 TOLERANCES OF FORM AND POSITION 0.20 aaa 0.20 bbb ...
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... Moisture Sensitivity Level Junction to Case Thermal Resistance, θ Junction to Air Thermal Resistance, θ j-a Psi Pb-free and RoHS Compliant Pb-free and RoHS Compliant No Yes 22208 - 8 January 2007 GS9060 Data Sheet Value 14mm x 14mm 80-pin LQFP JEDEC MS026 3 11.6°C/W j-c (at zero airflow) 39.9°C/W 0.6°C/W Yes Package ...
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... Date Changes and/or Modifications May 2004 Converted GS9060 to new template format. Moved ESD to maximum absolute ratings. Modified description of LOCKED pin in Data Through mode. Added note to host interface pins. Added Pb-free and Green availability and ordering information. Corrected minor typing errors November 2004 Added Solder Reflow Profile description ...