LH28F160BGR-TTL10 Sharp, LH28F160BGR-TTL10 Datasheet
LH28F160BGR-TTL10
Related parts for LH28F160BGR-TTL10
LH28F160BGR-TTL10 Summary of contents
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... Refer to the datasheet of LH28F160BV-TL/BVH-TL. In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device. ...
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PIN CONNECTIONS 60-BALL CSP 48-PIN TSOP (Type ...
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BLOCK ORGANIZATION This product features an asymmetrically-blocked architecture providing system memory integration. Each erase block can be erased independently of the others up to 100 000 times. For the address locations of the blocks, see the memory map in Fig. ...
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PIN DESCRIPTION SYMBOL TYPE ADDRESS INPUTS : Inputs for addresses during read and write operations. Addresses A -A INPUT 0 19 are internally latched during a write cycle. DATA INPUT/OUTPUTS : Inputs data and commands during CUI write cycles; outputs ...
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INTRODUCTION This datasheet contains LH28F160BG-TL/BGH-TL specifications. Section 1 provides a flash memory overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. LH28F160BG-TL/ BGH-TL flash memories documentation also includes ordering information ...
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Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase ...
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Top Boot FFFFF 4 k-Word Boot Block FF000 FEFFF 4 k-Word Boot Block FE000 FDFFF 4 k-Word Parameter Block FD000 FCFFF 4 k-Word Parameter Block FC000 FBFFF 4 k-Word Parameter Block FB000 FAFFF 4 k-Word Parameter Block FA000 F9FFF 4 ...
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PRINCIPLES OF OPERATION The LH28F160BG-TL/BGH-TL Smart 3 flash memories include an on-chip WSM to manage block erase and word write functions. It allows for : fixed power supplies during block erasure and word write, and minimal processor overhead with ...
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... IH -DQ ) are SHARP’s flash memories allow proper CPU 0 15 initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
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The CUI does not occupy an addressable memory location written when WE# and CE# are active. The address and data needed to execute a command are latched on the rising edge of WE# or CE# (whichever goes high ...
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... Attempts to issue a block erase or word write to a boot block while WP Either 40H or 10H is recognized by the WSM as the word write setup. 7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used LH28F160BG-TL/BGH-TL (NOTE 7) ...
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Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
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The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in ...
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The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register ...
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Table 4 Write Protection Alternatives OPERATION V RP# WP All Blocks Locked All Blocks Locked. Block Erase All Blocks Unlocked > V PPLK V 2 Boot Blocks Locked. ...
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Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7 = Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register ...
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Start Write 40H or 10H, Address Write Word Data and Address Read Status Register Suspend Word No Write Loop 0 Suspend SR.7 = Word Write Yes 1 Full Status Check if Desired Word Write Complete FULL STATUS CHECK PROCEDURE Read ...
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Start Write B0H Read Status Register 0 SR Block Erase SR.6 = Completed 1 Read Read Word Write or Word Write? Read Array Data Word Write Loop No Done? Yes Write D0H Write FFH Block Erase Resumed ...
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Start Write B0H Read Status Register 0 SR Word Write SR.2 = Completed 1 Write FFH Read Array Data No Done Reading Yes Write D0H Write FFH Read Word Write Resumed Array Data Fig. 6 Word Write ...
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... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three- line control provides for : a. Lowest possible memory power consumption. b. Complete assurance that data bus contention will not occur. ...
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V clear the status register. IL The CUI latches commands issued by system software and is not altered by V transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power- down ...
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... Output Capacitance OUT NOTE : 1. Sampled, not 100% tested. NOTICE : The specifications are subject to change without notice. Verify with your local SHARP sales office that you have the latest datasheet before finalizing a design. WARNING : Stressing the device beyond the Absolute Maximum (NOTE 1) " ...
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AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7 V for a logic "1" and 0.0 V for a Logic "0". Input timing begins, and output timing ends, at 1.35 V. Input rise and ...
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DC CHARACTERISTICS SYMBOL PARAMETER I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down Current CCD Read Current CCR Word Write Current CCW ...
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DC CHARACTERISTICS (contd.) SYMBOL PARAMETER V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage (TTL) OH1 V Output High Voltage (CMOS) OH2 V Lockout Voltage during PP V PPLK ...
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AC CHARACTERISTICS - READ-ONLY OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV ...
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Standby V IH ADDRESSES ( CE# ( OE# ( WE# ( High Z DATA (D/Q) (DQ - ...
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AC CHARACTERISTICS FOR WE#-CONTROLLED WRITE OPERATIONS V = 2 +70 • VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# ...
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V IH ADDRESSES ( CE# ( ELWL V IH OE# ( WE# ( High Z DATA (D/ PHWL ...
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AC CHARACTERISTICS FOR CE#-CONTROLLED WRITE OPERATIONS • 2 +70˚C or – VERSIONS SYMBOL PARAMETER t Write Cycle Time AVAV t RP# High Recovery to CE# Going ...
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V IH ADDRESSES ( WE# ( WLEL V IH OE# ( CE# ( High Z DATA (D/ PHEL IL ...
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RESET OPERATIONS High Z RY/BY# ( RP# ( High Z RY/BY# ( RP RP# ( Fig. ...
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BLOCK ERASE AND WORD WRITE PERFORMANCE • 2 +70°C or – SYMBOL PARAMETER t 32 k-Word Block WHQV1 Word Write Time t 4 k-Word Block EHQV1 ...
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... ORDERING INFORMATION Product line designator for all SHARP Flash products (H) E Device Density 160 = 16 M-bit Architecture B = Boot Block Power Supply Type G = Smart 3 Technology Operating Temperature Blank = –25 to +85 C OPTION ORDER CODE 1 LH28F160BGXX-XTL10 2 LH28F160BGXX-XTL12 LH28F160BG-TL/BGH-TL ...
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TSOP (TSOP048-P-1220 20.0 0.3 18.4 0.2 Package base plane 0.1 19.0 PACKAGING ...
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CSP (FBGA060/048-P-0811 0.1 S TYP. 1.1 TYP. 0.8 TYP. 0 TYP 0.2 11 0.03 0. ...