CY7B994V-7AC Cypress Semiconductor Corporation., CY7B994V-7AC Datasheet

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CY7B994V-7AC

Manufacturer Part Number
CY7B994V-7AC
Description
RoboClockII
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

Specifications of CY7B994V-7AC

Case
QFP-100L
Features
RoboClock
Cypress Semiconductor Corporation
Functional Block Diagram
• 12/100-MHz (CY7B993V), or 24/185-MHz (CY7B994V)
• Matched pair outputs skew <200 ps
• Zero input-to-output delay
• 18 LVTTL 50% duty-cycle outputs capable of driving
• Commercial Temp. Range with 16 outputs at 185 MHz
• Industrial Temp. Range with 6 outputs at 185 MHz
• 3.3V LVTTL/LV Differential (LVPECL), Fault Tolerant and
• Phase adjustments in 625/1300 ps steps up to ±10.4 ns
• Multiply/Divide ratios of (1–6, 8, 10, 12):(1–6, 8, 10, 12)
• Operation up to 12x input frequency
• Individual Output Bank disable for aggressive power
• Output high-impedance option for testing purposes
• Fully integrated PLL with Lock Indicator
• Low Cycle-to-Cycle Jitter (<100 ps peak-peak)
• Single 3.3V ± 10% supply
• 100-Pin TQFP package
output operation
50
Hot Insertable reference inputs
management and EMI reduction
terminated lines
,,
is a trademark of Cypress Semiconductor Corporation.
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High-Speed Multi-Phase PLL Clock Buffer
3901 North First Street
PRELIMINARY
Functional Description
The CY7B993V and CY7B994V High-Speed Multi-Phase PLL
Clock Buffers offer user-selectable control over system clock
functions. This multiple-output clock driver provides the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer and communication systems.
Eighteen configurable outputs can each drive terminated
transmission lines with impedances as low as 50 while deliv-
ering minimal and specified output skews at LVTTL levels. The out-
puts are arranged in five banks. Banks 1 to 4 of four outputs
allow a divide function of 1 to 12, while simultaneously allowing
phase adjustments in 625 ps–1300 ps increments up to 10.4
ns. One of the output banks also includes an independent
clock invert function. The feedback bank consists of two out-
puts, which allows divide-by functionality from 1 to 12 and lim-
ited phase adjustments. Any one of these eighteen outputs
can be connected to the feedback input as well as driving other
inputs.
Selectable reference input is a fault tolerance feature which
allows smooth change over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
San Jose
RoboClock
CA 95134
,,
™ CY7B994V
CY7B993V
August 8, 2000
408-943-2600

Related parts for CY7B994V-7AC

CY7B994V-7AC Summary of contents

Page 1

... RoboClock PRELIMINARY High-Speed Multi-Phase PLL Clock Buffer Functional Description The CY7B993V and CY7B994V High-Speed Multi-Phase PLL Clock Buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the sys- tem integrator with functions necessary to optimize the timing of high-performance computer and communication systems. ...

Page 2

... Pin Configurations PRELIMINARY 100-Pin TQFP 2 ,, RoboClock ™ CY7B993V CY7B994V ...

Page 3

... GND GND GND GND VCCQ GND GND VCCQ DIS1 VCCN VCCN GND VCCN 3QA0 3QA1 GND 3 RoboClock CY7B993V CY7B994V VCCQ FBKA– FBKA+ FBKB– FBSEL REFA+ GND GND REFA– VCCQ REFSEL REFB– FS VCCN REFB+ (3_level) FBF0 VCCN ...

Page 4

... Clock Output: These outputs provide numerous divide and phase select functions deter- mined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs. Output Buffer Power: Power supply for each output pair. Internal Power: Power supply for the internal circuitry. Device Ground. , LOW indicates a connection to GND, and MID indicates an open connection. Internal termination CC / RoboClock ™ CY7B993V CY7B994V ). NOM ...

Page 5

... NOM There are two versions of the RoboClock (CY7B993V) where f ranges from 12 MHz to 100 MHz, NOM and a high-speed device (CY7B994V) which ranges from 24 MHz to 200 MHz. The FS setting for each device is shown in Table 1. The f frequency is seen on “divide-by-one” outputs. For the ...

Page 6

... RoboClock CY7B993V CY7B994V skew. The U matrix will shift with respect U , then the whole matrix is shifted forward U . Thus an output programmed with 8t U with respect to REF. U [5] ,, ™ of skew U ...

Page 7

... Figure 2 shows that at 85°C, the maximum number of outputs that can operate at 185 MHz is 6; and at 70°C, the maximum number of outputs that can operate at 185 MHz is 16 (with 25-pF load and 0-m/s air flow RoboClock ™ CY7B993V CY7B994V ...

Page 8

... Max Max [6] Min. < Min. < Min. < RoboClock CY7B993V CY7B994V +125 +125 C 0.5V to +4.6V 0. Ambient Temperature +70 C 3.3V 10% – +85 C 3.3V 10% Min. Max. = – Min Min ...

Page 9

... For any other frequencies and load conditions the following equation can be used to calculate the maximum output CC current: TBD measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (f CCI CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE are asserted to the HIGH state. PRELIMINARY Test Conditions = ...

Page 10

... UI = Unit Interval. Examples full period. 0.1UI is 10% of period. PRELIMINARY [9, 10, 11, 12, 13] Description CY7B993V CY7B994V [14, 15] [14, 15] and SKEW1 [14, 15, 16] [17] [18] [18] [13] [21] [21] [22 RoboClock CY7B993V CY7B994V CY7B993/4V-5 CY7B993/4V-7 Min. Max. Min. Max. Unit 100 100 MHz 185 185 MHz 185 185 ps 250 350 ps 550 750 ...

Page 11

... These figures are for illustrations only. The actual ATE loads may vary. PRELIMINARY [9, 10, 11, 12, 13] (continued) Description [14, 23] [14, 23] [24] for GND for t ). For t and t CC OZL OZH OZL OZH 11 RoboClock CY7B993V CY7B994V CY7B993/4V-5 CY7B993/4V-7 Min. Max. Min. Max. Unit 1.0 10 1.0 10 1.0 10 1.0 10 [23] [25] [23] [25] ...

Page 12

... AC Timing Diagrams PRELIMINARY 12 ,, RoboClock ™ CY7B993V CY7B994V ...

Page 13

... CY7B994V-5BBC 500 185 CY7B994V-5AI 700 100 CY7B993V-7AC 700 185 CY7B994V-7AC Document #: 38-00747-G 3DFNDJH 'LDJUDPV 3LQ 7KLQ 3ODVWLF 4XDG )ODW 3DFN 74)3 $ PRELIMINARY Package Name Package Type A100 100-Lead Thin Quad Flat Pack Commercial A100 100-Lead Thin Quad Flat Pack Industrial ...

Page 14

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY ,, RoboClock ™ CY7B994V CY7B993V  ...

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