AM79C940JC Advanced Micro Devices, AM79C940JC Datasheet
AM79C940JC
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AM79C940JC Summary of contents
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FINAL Am79C940 Media Access Controller for Ethernet (MACE DISTINCTIVE CHARACTERISTICS Integrated Controller with 10BASE-T transceiver and AUI port Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards 84-pin PLCC and 100-pin PQFP Packages 80-pin Thin Quad Flat Pack (TQFP) package available for ...
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AMD Additional features also enhance over-all system design. The individual transmit and receive FIFOs optimize system overhead, providing substantial latency during packet transmission and reception, and minimizing intervention during normal network error recovery. The integrated Manchester encoder/decoder eliminates the need ...
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RELATED PRODUCTS Part No. Description Am7996 IEEE 802.3/Ethernet/Cheapernet Transceiver Am79C90 CMOS Local Area Network Controller for Ethernet (C-LANCE) Am79C98 Twisted Pair Ethernet Transceiver (TPEX) Am79C100 Twisted Pair Ethernet Transceiver Plus (TPEX+) Am79C981 Integrated Multiport Repeater Plus Am79C987 Hardware Implemented Management ...
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AMD TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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External Address Detection Interface (EADI) General Purpose Serial Interface (GPSI) IEEE 1149.1 Test Access Port Interface Slave Access Operation . . . . . . . . . . . . . . . . . . . . . ...
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AMD Physical Address (PADR [47–00]) Missed Packet Count (MPC) Runt Packet Count (RNTPC) Receive Collision Count (RCVCC) User Test Register (UTR) Reserved Test Register 1 (RTR1) Reserved Test Register 2 (RTR2) Register Table Summary Register Bit Summary 16-Bit Registers 8-Bit ...
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... DBUS3 25 DBUS4 DBUS5 28 DBUS6 29 DBUS7 30 31 DBUS8 DBUS9 Am79C940 MACE MACE Am79C940JC Am79C940 AMD XTAL2 XTAL1 TXD+ 69 TXP+ ...
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AMD CONNECTION DIAGRAMS PQR 100 PQFP Package SRDCLK 5 EAM SRD 8 SF/BD RESET 9 SLEEP INTR DBUS0 ...
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CONNECTION DIAGRAMS PQT 080 TQFP Package SRDCLK 1 EAM/R 2 SF/BD 3 RESET 4 SLEEP 5 6 DVDD INTR 7 ...
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AMD ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: AM79C940 V C DEVICE NUMBER/DESCRIPTION (include revision letter) Am79C940 Media Access Controller for ...
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PIN/PACKAGE SUMMARY PLCC Pin # Pin Name 1 DXCVR 2 EDSEL TXDAT+ 5 TXDAT– STDCLK 8 TXEN/TXEN 9 CLSN 10 RXDAT 11 RXCRS 12 SRDCLK EAM SRD 15 SF/BD RESET ...
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AMD PIN/PACKAGE SUMMARY (continued) PLCC Pin # Pin Name FDS 43 BE0 44 BE1 45 46 SCLK TDTREQ 47 RDTREQ 48 49 ADD0 50 ADD1 51 ADD2 52 ADD3 53 ADD4 54 R RXPOL 56 LNKST 57 58 ...
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PIN/PACKAGE SUMMARY (continued) PQFP Pin # Pin Name SRDCLK EAM SRD 8 SF/BD RESET 9 SLEEP 10 11 DVDD INTR DBUS0 ...
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AMD PIN/PACKAGE SUMMARY (continued) PQFP Pin # Pin Name 43 SCLK TDTREQ 44 RDTREQ 45 46 ADD0 47 ADD1 48 ADD2 49 ADD3 50 ADD4 R RXPOL 57 LNKST ...
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PIN/PACKAGE SUMMARY (continued) PQFP Pin # Pin Name 86 CI– DXCVR 91 EDSEL TXDAT+ 94 TXDAT– STDCLK 97 TXEN/TXEN 98 CLSN 99 RXDAT ...
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AMD PIN/PACKAGE SUMMARY (continued) TQFP Pin Number Pin Name Pin Function 1 SRDCLK Serial Receive Data Clock 2 EAM/R External Address Match/Reject 3 SF/BD Start Frame/Byte Delimiter RESET 4 Reset SLEEP 5 Sleep Mode 6 DVDD Digital Power INTR 7 ...
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PIN SUMMARY Pin Name Pin Function Attachment Unit Interface (AUI) DO+/DO– Data Out DI+/DI– Data In CI+/CI– Control In RXCRS Receive Carrier Sense TXEN Transmit Enable CLSN Collision DXCVR Disable Transceiver STDCLK Serial Transmit Data Clock SRDCLK Serial Receive Data ...
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AMD PIN SUMMARY (continued) Pin Name Pin Function External Address Detection Interface (EADI) SF/BD Start Frame/Byte Delimiter SRD Serial Receive Data EAM/R External Address Match/Reject SRDCLK Serial Receive Data Clock Host System Interface DBUS15–0 Data Bus ADD4–0 Address R/W Read/Write ...
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PIN DESCRIPTION Network Interfaces The MACE device has five potential network interfaces. Only one of the interfaces that provides physical net- work attachment can be used (active) at any time. Se- lection between the AUI, 10BASE-T, DAI or GPSI ports ...
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AMD TXEN/TXEN Transmit Enable (Output) When the AUI port is selected (PORTSEL [1–0] = 00), an output indicating that the AUI DO differential output has valid Manchester encoded data is presented. When the 10BASE-T port is selected (PORTSEL [1–0] = ...
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PORTSEL SLEEP [1– Notes: 1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, if ...
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AMD DXCVR Configuration—Normal Operation SLEEP LNKST ASEL Pin Bit Pin HIGH 1 1 LOW Note: RWAKE and ASEL are located in the PHY ...
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PORTSEL SLEEP [1– Notes: 1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14). 2. This pin should be externally terminated, if ...
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AMD EAM/R External Address Match/Reject (Input) The incoming frame will be received dependent on the receive operational mode of the MACE device, and the polarity of the EAM/R pin. The EAM/R pin function is programmed by use of the M/R ...
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HOST SYSTEM INTERFACE DBUS15–0 Data Bus ( Input/Output/3-state) DBUS contains read and write data to and from internal registers and the Transmit and Receive FIFOs. ADD4–0 Address Bus (Input) ADD is used to access the internal registers and FIFOs to ...
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AMD INTR Interrupt (Output, Open Drain) An attention signal indicating that one or more of the fol- lowing status flags are set: XMTINT, RCVINT, MPCO, RPCO, RCVCCO, CERR, BABL or JAB. Each interrupt source can be individually masked. No interrupt ...
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TMS, and TDI pins. SCLK must run for 5 cycles after the assertion of SLEEP. During the “Deep Sleep”, the SCLK input can be optionally suspended for maximum power savings. Upon exiting “Deep Sleep”, the hardware RESET pin must be ...
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AMD sort of operation are bridges and routers. Lack of perfect filtering in these applications forces the CPU to be more involved in filtering and thus either slows the forwarding rates achieved or forces the use of a more powerful ...
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FUNCTIONAL DESCRIPTION The Media Access Controller for Ethernet (MACE) chip embodies the Media Access Control (MAC) and Physi- cal Signaling (PLS) sub-layers of the 802.3 Standard. The MACE device provides the IEEE defined Attach- ment Unit Interface (AUI) for coupling ...
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AMD The Transmit FIFO data will not be overwritten until at least 512 data bits have been transmitted onto the net- work collision occurs within the slot time (512 bit time) window, the MACE device will generate a ...
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When neither BE0 nor BE1 are asserted, no data transfer will take place. DTV will not be asserted. Byte Alignment For FIFO Read Operations BE0 BE1 BSWP DBUS7– ...
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AMD ensure the XMTFIFO does not underflow during the transmit process, versus using the default XMTSP value. Note that if 64 single byte writes are executed on the XMTFIFO, and the XMTSP is set to 64-bytes, the transmission will commence, ...
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The first assertion of RDTREQ for a packet will occur af- ter the longer of the following two conditions is met: 64-bytes have been received (to assure runt pack- ets and packets experiencing collision within the slot time will be ...
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AMD sub-system and the Manchester Encoder/Decoder (MENDEC). The MAC engine is fully compliant to Section 4 of ISO/ IEC 8802-3 (ANSI/IEEE Standard 1990 Second edition) and ANSI/IEEE 802.3 (1985). The MAC engine provides enhanced features, pro- grammed through the Transmit ...
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MACE device activity. On completion of transmission, the MACE device will re- port the Transmit Frame Status for the frame. The exact number of transmission retry attempts is reported (ONE, MORE ...
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AMD dium. An initial period shorter than 2/3 of the interval is permissible including zero.” The MAC engine implements the optional receive two part deferral algorithm, with a first part inter-frame- spacing time of 6.0 s. The second part of ...
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XMTFIFO. The RTRY condition will cause the de- assertion of TDTREQ, and the assertion of the INTR pin, providing the XMTINTM bit is cleared collision is ...
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AMD Parameter 1. Parallel Resonant Frequency 2. Resonant Frequency Error ( pF) 3. Change in Resonant Frequency With Respect To Temperature ( pF)* 4. Crystal Capacitance 5. Motional Crystal Capacitance (C1) 6. Series Resistance 7. Shunt ...
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DI Input Signal Conditioning Transient noise pulses at the input data stream are re- jected by the Noise Rejection Filter. Pulse width rejec- tion is proportional to transmit data rate. DC inputs more negative than minus 100 mV are also ...
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AMD below. The differential input impedance, Z common-mode input impedance, Z ICM that the Ethernet specification for cable termination im- pedance is met using standard 1% resistor terminators. DI+ MACE DI- Collision Detection A transceiver detects the collision condition on ...
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DAI interface must not loop back the transmit data (presented by the MACE device) on the TXDAT pins to the RXDAT pin. Neither should the transceiver assert the RXCRS pin when transmitting data to the network. ...
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AMD extraneous noise, primarily caused by coupling from co- resident services (crosstalk). For this reason rec- ommended that when using the Low Receive Threshold option that the service should be installed on 4-pair ca- ble only. Multi-pair cables ...
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ETD polar- ity. On receipt of the first packet with valid ETD following re- set or Link Fail, the MACE device will utilize ...
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AMD internal MENDEC activity), and allow the RXCRS pin to indicate the current state of the RXD pair. If there is no receive activity on RXD , only CLSN will be active dur- ing jabber detect. If there is RXD ...
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Internal/External Address Recognition Capabilities EAM/R PROM M General Purpose Serial Interface (GPSI) The GPSI port provides the signals necessary to pre- sent an interface consistent with the ...
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AMD Other Data Registers BYPASS REG (1 bit) Device Identification Register (32 bits) Bits 31–28: Version (4 bits) Bits 27–12: Part number (16 bits) is 9400H Bits 11–1: Manufacturer ID (11 bits). The manufacturer ID code for AMD is 00000000001 ...
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FIFO Direct mode, the MACE device will place EOF in a high impedance state. RDTREQ should be sampled on the falling edge of SCLK. The assertion of RDTREQ is programmed by RCVFW, and the de-assertion is modified dependent ...
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AMD register and the Transmit Frame Control register can be re-programmed if the MACE device is not transmitting. Transmit FIFO Write The Transmit FIFO is accessed by performing a host generated write sequence on the MACE device. See the Slave ...
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Depending on the bus latency of the system, XMTFW can be set to ensure that the Transmit FIFO does not underflow before more data is written into the FIFO. When the entire frame is in the FIFO, TDTREQ will re- ...
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AMD Preamble SYNCH 1010....1010 Bits Bits Transmit FCS Generation Automatic generation and transmission of FCS for a transmit frame depends on the value of DXMTFCS (Dis- able Transmit FCS) when the EOF is asserted indicating the last ...
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XMTFW value in the FIFO Configuration Control register whole frame does reside in the FIFO, the read pointer will be moved to the start of the next frame or free location in the FIFO, and the write ...
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AMD (nominal 10 MHz sequence returned via the CI pair, within a 40 network bit time period after DI goes inactive. If the CI input is not asserted within the 40 net- work bit time period following the ...
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Receive Function Programming The Receive Frame Control register allows program- ming of the automatic pad field stripping feature and the configuration of the Match/Reject (M/R) pin. ASTRP RCV and M/R must be static when the receive function is enabled (ENRCV ...
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AMD Receive frames which have a length field of 46 bytes or greater will be passed to the host unmodified. Since any valid Ethernet Type field value will always be greater than a normal 802.3 Length field, the MACE de- ...
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Receive FIFO with no host intervention (the state of the RPA bit in the User Test Register; or the RCVFW bits in the FIFO Configu- ration Control ...
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AMD data without addition of an FCS field, and the FCS will be calculated and verified at the receiver. The loopback facilities of the MACE device allow full op- eration to be verified without disturbance to the network. Loopback operation ...
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USER ACCESSIBLE REGISTERS The following registers are provided for operation of the MACE device. All registers are 8-bits wide unless other- wise stated. Note that all reserved register bits should be written as zero. Receive FIFO (RCVFIFO) RCVFIFO [15–0] This ...
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AMD activation of the RESET pin or SWRST bit. DXMTFCS is sam- pled only when EOF is asserted during a Transmit FIFO write. Bit Name Description Bit 2–1 RES Reserved. Read as zeroes. Al- ways write as zeroes. Bit 0 ...
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Transmit Retry Count (XMTRC) The Transmit Retry Count should be read only in re- sponse to a hardware interrupt request (INTR asserted) when XMTINT is set in the Interrupt Register, or after XMTSV is set in the Poll Register.The register ...
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AMD Bit 0 ASTRP RCV Auto Strip Receive. ASTRP RCV enables the automatic pad strip- ping feature. The pad and FCS fields will be stripped from re- ceive frames and not placed in the FIFO. ASTRP RCV is set by ...
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FCS will not be set if OFLO is set. Bit 3–0 RCVCNT The Receive Message Byte [11:8] Count indicates the number of whole bytes in the received mes- sage from the network. RCVCNT is 12 bits ...
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AMD vated if the corresponding mask bit BABLM = 0. BABL is READ/CLEAR only, and is set by the MACE device and reset when read. Writing has no effect also cleared by activa- tion of the RESET pin ...
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Transmit Frame Status. The INTR pin will be acti- vated if the corresponding mask bit XMTINTM = 0. XMTINT is READ/CLEAR only set by the MACE device and reset when ...
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AMD Bit 5 RDTREQ Receive Data Transfer Request. An internal indication of the current request status of the Re- ceive FIFO. RDTREQ is set when the external RDTREQ sig- nal is asserted. Bit 4–0 RES Reserved. Read as zeroes. Always ...
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When us- ing the burst mode, TDTREQ will not be de-asserted until only a single write cycle can be per- formed. See the FIFO Sub-sys- tem section for additional details. Bit 5-4 RCVFW Receive FIFO [1–0] RCVFW ...
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AMD TDTREQ will be asserted identi- cally in both normal and burst modes, when there is sufficient space in the XMTFIFO to allow the specified number of write cycles to occur (programmed by the XMTFW bits). Cleared by activation of ...
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RDTREQ. If ENRCV is cleared during receive activity and remains cleared for a long time and if the tail end of the re- ceive frame currently in progress is longer than the amount of space available in the ...
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AMD not implement Link Test, this function can be disabled by set- ting the DLNKTST bit. With Link Test disabled (DLNKTST = 1), the data driver, receiver and loopback functions as well as col- lision detection remain enabled irrespective of ...
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ADDRCHG RES RES RES RES PHYADDR Bit Name Description Bit 7 ADDRCHG Address Change. When set, al- lows the physical and/or logical address to be read or pro- grammed. When ADDRCHG is set, ENRCV will be cleared, the MPC will ...
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AMD Received Message Destination Address 32-Bit Resultant CRC 31 26 CRC GEN 63 SEL 64 MUX 6 MATCH = 1: Packet Accepted MATCH = 0: Packet Rejected Logical Address Match Logic Am79C940 0 Logical Address ...
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Physical Address (PADR [47–00]) PADR [47–00] This 48-bit value represents the unique node value as- signed by the IEEE and used for internal address com- parison. After a hardware or software reset and before the ENRCV bit in the MAC ...
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AMD Receive Collision Count (RCVCC) (REG ADDR 27) RCVCC [7–0] The Receive Collision Count (RCVCC read only 8-bit counter, incremented when the receiver detects a collision on the network. Note that the RCVCC value re- turned in the ...
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Loopback Functions Loop [1–0] Function 00 No Loopback 01 External Loopback 10 Internal Loopback, excludes MENDEC 11 Internal Loopback, includes MENDEC External loopback allow the MACE device to transmit to the physical medium, using either the AUI, 10BASE-T, DAI or ...
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AMD Register Table Summary Address Mnemonic 0 RCVFIFO 1 XMTFIFO 2 XMTFC 3 XMTFS 4 XMTRC 5 RCVFC 6 RCVFS 7 FIFOFC IMR BIUCC 12 FIFOCC 13 MACCC 14 PLSCC 15 PHYCC 16 CHIPID ...
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Register Bit Summary 16-Bit Registers 0 1 8-Bit Registers Address 2 DRTRY RES 3 XMTSV UFLO 4 EXDEF RES 5 RES RES 6 RCVFC [3– JAB BABL 9 JABM BABLM 10 XMTSV TDTREQ 11 RES BSWP 12 XMTFW ...
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AMD Programmer’s Register Model Addr Mnemonic 0 RCVFIFO Receive FIFO—16 bits 1 XMTFIFO Transmit FIFO—16 bits 2 XMTFC Transmit Frame Control 80 DRTRY 08 DXMTFCS 01 APADXMT 3 XMTFS Transmit Frame Status 80 XMTSV 40 UFLO 20 LCOL 10 MORE ...
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Programmer’s Register Model (continued) Addr Mnemonic 9 IMR Interrupt Mask Register 80 JABM 40 BABLM 20 CERRM 10 RCVCCOM 08 RNTPCOM 04 MPCOM 02 RCVINTM 01 XMTINTM 10 PR Poll Register 80 XMTSV 40 TDTREQ 20 RDTREQ 11 BIUCC Bus ...
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AMD Programmer’s Register Model (continued) Addr Mnemonic 14 PLSCC Physical Layer Signalling (PLS) Configuration Control 08 XMTSEL 06 PORTSEL [1:0]—Port Select (2 bits ENPLSIO Enable Status 15 PHYCC Physical Layer (PHY) Configuration Control 80 LNKFL ...
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Programmer’s Register Model (continued) Addr Mnemonic 30 — Reserved 31 — Reserved SYSTEM APPLICATIONS Host System Examples Motherboard DMA Controller The block diagram shows the MACE device interfacing to a 8237 type DMA controller. Two external latches are used to ...
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AMD CLK SCLK DREQ0 DREQ1 DACK0 DACK1 8237 ADSTB DB[7:0] A[7:0] IOW CSMACE D[7:0] Q[7:0] ’373 D[7:0] D[7:0] Q[7:0] ’373 LATCHHIGHADR D[15:0] A[23:0] System Interface – Motherboard DMA Example EOP Am79C940 SCLK RDTREQ ...
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PC/AT Ethernet Adapter Card SA19–SA0 Remote Boot PROM I S SD7–SD0 SD15–SD8 CAM System Interface – Simple PC/AT Ethernet Adapter Card Example IEEE Address PROM D7–D0 Am79C940 D15–D8 Am79C940 AMD AUI DB15 RJ45 TP GPSI/DAI Header ...
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AMD NETWORK INTERFACES External Address Detection Interface (EADI) The External Address Detection Interface can be used to implement alternative address recognition schemes outside the MACE device, to complement the physical, logical and promiscuous detection supported internally. EADI Pins SRD SRDCLK ...
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Attachment Unit Interface (AUI) The AUI can drive standard drop cable to allow the transceiver to be remotely located typi- cally the case in IEEE 803.3 10BASE5 or thick Ether- net installations. For ...
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AMD 10BASE-T/Twisted-Pair Ethernet System CPU I/O Processor AUI-10BASE-T/Unshielded Twisted-Pair Interface 84 Other Slave Am79C9416 I/O Device(s) Am79C940 MACE i.e. SCSI Slave Peripheral Bus Am79C940 RJ45 Unshielded Twisted-Pair 16235C-16 ...
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ANLG +5 V 0.1 F AVDD AVSS TXD+ TXP+ TXD– TXP– RXD+ RXD– LNKST RXPOL Am79C940 DXCVR DO+ DO– DI+ DI– CI+ CI– 40.2 0.1 F Optional Notes: 1. Compatible filter modules, with a brief description of package type and ...
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AMD ANLG +5 V 0.1 F AVDD AVSS TXD+ TXP+ TXD– TXP– RXD+ RXD– LNKST RXPOL Am79C940 DO+ DO– DI+ DI– CI+ CI– 40.2 0.1 F Optional : Notes 1. Compatible filter modules, with a brief description of package type ...
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MACE Compatible 10BASE-T Filters and Transformers The table below provides a sample list of MACE com- patible 10BASE-T filter and transformer modules avail- able from various vendors. Contact the respective manufacturer for a complete and updated listing of components. Manufacturer ...
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AMD MACE Compatible DC/DC Converters The table below provides a sample list of MACE com- patible DC/DC converters available from various ven- dors. Contact the respective manufacturer for a complete and updated listing of components. Manufacturer Part # Halo Electronics ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature Under Bias . . . . . . . . . . . . . . . . . . . . ...
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AMD DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description VAOCM DO Common Mode Output Voltage VODI DO Differential Output Voltage Imbalance VATH Receive Data Differential Input Threshold VASQ DI and CI Differential Input Threshold ...
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DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified (continued) Parameter Symbol Parameter Description VRXDTH RXD Switching Threshold VTXH TXD and TXP Output HIGH Voltage VTXL TXD and TXP Output LOW Voltage VTXI TXD and TXP Differential Output Voltage Imbalance ...
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AMD AC CHARACTERISTICS Parameter No. Symbol Parameter Description Clock and Reset Timing 1 t SCLK period SCLK 2 t SCLK LOW pulse width SCLKL 3 t SCLK HIGH pulse width SCLKH 4 t SCLK rise time SCLKR 5 t SCLK ...
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AC CHARACTERISTICS (continued) Parameter No. Symbol Parameter Description AUI Timing 53 tDOTD XTAL1 (externally driven output 54 tDOTR DO rise time (10% to 90%) 55 tDOTF DO fall time (10% to 90%) 56 tDOETM DO rise and fall ...
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AMD AC CHARACTERISTICS (continued) Parameter No. Symbol Parameter Description GPSI Clock Timing 17 tSTDC STDCLK period 18 tSTDCL STDCLK low pulse width 19 tSTDCH STDCLK high pulse width 20 tSTDCR STDCLK rise time 21 tSTDCF STDCLK fall time 22 tSRDC ...
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AC CHARACTERISTICS (continued) Parameter No. Symbol Parameter Description IEEE 1149.1 Timing 109 tTCLK TCK Period, 50% duty cycle (+5%) 110 tsu1 TMS setup to TCK 111 tsu2 TDI setup to TCK 112 thd1 TMS hold time from TCK 113 thd2 ...
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AMD BIU Output Valid Delay vs. Load Chart nom+4 nom BIU Output Valid Delay from SCLK (ns) nom–4 nom–8 KEY TO SWITCHING WAVEFORMS WAVEFORM 100 C (pF) L INPUTS OUTPUTS Must be Will be Steady Steady May ...
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SWITCHING TEST CIRCUITS Sense Point DO+ DO– TXD+ TXD– Includes Test Jig Capacitance 16235C-20 Normal and Three-State Outputs AV DD 52.3 Test Point 154 100 16235C-21 AUI DO Switching Test Circuit ...
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AMD TXP+ TXP– Includes Test Jig Capacitance AC WAVEFORMS 3 SCLK 4 RESET 11 XTAL1 715 Test Point 715 100 16235C-23 TXP Outputs Test Circuit Clock ...
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AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) 31 ADD[4:0] R FDS DBUS[15:0] 50 Word N DTV EOF BE0 Host System Interface—2-Cycle Receive FIFO/Register Read Timing ...
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AMD AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) 31 ADD[4:0] R FDS 35 DBUS[15:0] 50 DTV EOF BE0 Host System Interface—3-Cycle Receive FIFO/Register Read Timing ...
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AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) 31 ADD4–0 R FDS DBUS15–0 DTV 37 EOF BE0 Host System Interface—2-Cycle Transmit FIFO/Register Write Timing S1 S2 ...
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AMD AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) 31 ADD[4:0] R DBUS[15:0] DTV EOF BE0 Host System Interface—3-Cycle Transmit FIFO/Register Write Timing SCLK ...
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AC WAVEFORMS SCLK (EDSEL = 0) SCLK (EDSEL = 1) EOF TDTREQ Notes: 1. TDTREQ will be asserted for two write cycles (4 SCLK cycles) minimum. 2. TDTREQ will deassert 1 SCLK ...
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AMD XTAL1 STDCLK TXEN 1 1 TXDAT+ (Note 1) DO+ DO– DO± 1 bit (n–2) Note: TXDAT+ is the internal version of the signal, and is shown for clarification only. AUI Transmit Timing—End of Packet (Last Bit = 0) XTAL1 ...
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DO± AUI Transmit Timing—End Transmit Delimiter (ETD) Bit Cell 1 1 (Note 1) 59 DI± V ASQ BCC RXCRS IVCO_ENABLE IVCO SRDCLK SRD Notes: 1. Minimum pulse width >45 ns with amplitude > –160 mV. 2. SRD first decoded bit ...
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AMD Bit Cell (n– DI± V ASQ BCC RXCRS IVCO SRDCLK SRD Notes: 1. RXCRS deasserts in less than 3 bit times after last DI ± rising edge. 2. Start of next packet reception (2 bit times). 3. ...
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DO± TXEN CI+ CI- 80 CLSN DO± CI+ CI- CLSN = 0 AUI SQE Test Timing 79 AUI Collision Timing 66 67 Am79C940 AMD 16235C-38 16235C-39 107 ...
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AMD STDCLK BCB 72 TXDAT± TXDAT+ 95 TXDAT- 72 TXEN RXDAT 100 RXCRS 108 BCB BCB BCB BCB BCB 97 96 DAI Port Transmit Timing DAI Port Receive Timing Am79C940 BCB BCB 99 16235C-40 101 16235C-41 ...
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TXDAT+ TXDAT- TXEN RXDAT RXCRS 102 CLSN SRDCLK SRD SF/BD 85 EAM/R Note: First assertion of EAM/R must occur after bit 2/3 boundary of preamble. 79 DAI Port Collision Timing Destination Address Byte 1 BIT BIT BIT BIT BIT BIT ...
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AMD SRDCLK SRD SF/BD 85 Destination Address Byte 6 SRDCLK SRD BIT BIT 5 6 SF/BD EAM 110 Last Byte of Message 86 EADI Feature—End of Packet Timing Source Address Byte 1 BIT BIT BIT BIT BIT BIT BIT 3 ...
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Byte 64 (Data Byte 51) SRDCLK BIT BIT BIT SRD 4 5 SF/BD 91 EAR STDCLK 72 TXDAT+ 70 TXEN RXCRS Note: During transmit, the RXCRS input must be asserted (high) and remain active-high after TXEN goes active (high). If ...
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AMD SRDCLK RXDAT RXCRS STDCLK 72 TXDAT+ 70 TXEN CLSN 112 GPSI Receive Timing GPSI Collision Timing Am79C940 16235C-48 16235C-49 ...
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TCK TMS TDI TDO System Output TXD+ TXP+ TXD– TXP– t XMTON TXEN Note 1 Note: 1. Parameter is internal to the device. tsu1 thd1 tsu2 thd2 IEEE 1149.1 TAP Timing t TR 10BASE-T Transmit Timing Am79C940 AMD td1 td2 ...
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AMD RXD t RCVON RXCRS TXD RXD t COLON CLSN 114 10BASE-T Receive Timing 10BASE-T Collision Timing Am79C940 V TSQ+ V TSQ– t RCVOFF 16235C-52 t COLOFF 16235C-53 ...
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PWPLP TXD+ TXP+ TXD– TXP– t PWLP 10BASE-T Idle Link Test Pulse RXD 10BASE-T Receive Thresholds (LRT = 0) RXD 10BASE-T Receive Thresholds (LRT = 1) t PERLP V THS+ V THS– V LTHS+ V LTHS– Am79C940 AMD 16235C-54 ...
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APPENDIX A Logical Address Filtering For Ethernet The purpose of logical (or group or multicast) addresses is to allow a group of nodes in a network to receive the same message. Each node can maintain a list of multi- cast ...
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AMD MAPPING OF LOGICAL ADDRESS TO FILTER MASK LADRF Byte # Bit # Bit ...
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APPENDIX B APPENDIX B BSDL Description of Am79C940 MACE JTAG Structure entity Am79C940 is generic (PHYSICAL_PIN_MAP : string := ”undefined”); port ( DO0,DO1,DTV_L,INTR_L,LNKST_L,DXRCV_L,RDTREQ_L,RXPOL_L,SF_BD,SRD, TDO,TDTREQ_L,TXD0,TXD1,TXDAT0,TXP0,TXP1,XTAL2 : out bit; BE0_L,BE1_L,CI0,CI1,CS_L,DI0,DI1,EAM_R_L,EDSE L,FDS_L,RESET_L,RXD0, RXD1,R_W_L,SCLK,SLEEP_L,TCLK,TC_L,TDI,TMS,XTAL1 : in bit; ADD : in bit_vector (4 downto 0); ...
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AMD “DVSS2:92,” & “TXDAT1:93, TXDAT0:94,” & “DVSSP:95,” & “STDCLK:96, TXEN_L:97, CLSN:98, RXDAT:99, RXCRS:100); constant PLCC_PACKAGE : PIN_MAP_STRING := “SRDCLK:12, EAM_R_L:13, SRD:14, SF_BD:15, RESET_L:16, SLEEP_L:17,” & “DVDDP:18,” & “INTR_L:19, TC_L:20,” & “DBUS:(39, 38, 36, 35, 34, 33, 32, 31, 30, 29, ...
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INSTRUCTION_PRIVATE of am79c940 : entity is “Selftst”; attribute IDCODE_REGISTER of am79c940 : entity is “0000” & – 4 bit version “1001010000000000” & – 16 bit part number ”00000000001” & – 11 bit manufacturer “1”; – mandatory LSB attribute REGISTER_ACCESS ...
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AMD “61 (BC_1, *, “60 (BC_1, RESET_L, “59 (BC_1, SLEEP_L, “58 (BC_1, INTR_L, “57 (BC_1, *, “56 (BC_1, TC_L, “55 (BC_1, DBUS(0), “54 (BC_1, DBUS(0), “53 (BC_1, DBUS(1), “52 (BC_1, DBUS(1), “51 (BC_1, DBUS(2), “50 (BC_1, DBUS(2), “49 (BC_1, DBUS(3), ...
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ADD(1), “7 (BC_1, ADD(2), “6 (BC_1, ADD(3), “5 (BC_1, ADD(4), “4 (BC_1, R_W_L, “3 (BC_1, CS_L, “2 (BC_1, RXPOL_L, “1 (BC_1, LNKST_L, “0 (BC_1, *, end am79c940 input, 0),” & input, 0),” & input, 0),” & input, 0),” ...