CDP1802ACE Intersil Corporation, CDP1802ACE Datasheet

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... Easy to Use Instructions - - Ordering Information PART NUMBER 5V - 3.2MHz CDP1802ACE CDP1802BCE CDP1802ACEX CDP1802BCEX CDP1802ACQ CDP1802BCQ CDP1802ACD CDP1802ACDX CDP1802BCDX CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 321-724-7143 Intersil (and design trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved ...

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CDP1802A, CDP1802AC, CDP1802BC Pinouts 40 LEAD PDIP (PACKAGE SUFFIX E) 40 LEAD SBDIP (PACKAGE SUFFIX D) TOP VIEW CLOCK 1 WAIT 2 CLEAR SC1 5 SC0 6 MRD 7 BUS 7 8 BUS 6 9 BUS 5 ...

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CDP1802A, CDP1802AC, CDP1802BC Block Diagram MEMORY ADDRESS LINES MA6 MA7 MA5 MA3 MA1 B ALU INCR/ DECR DF D 8-BIT BIDIRECTIONAL DATA BUS I/O REQUESTS I/O FLAGS DMA OUT MA4 MA2 MA0 EF1 EF3 DMA EF2 EF4 IN INT MUX ...

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CDP1802A, CDP1802AC, CDP1802BC Absolute Maximum Ratings DC Supply Voltage Range (All Voltages Referenced to V Terminal) SS CDP1802A ...

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CDP1802A, CDP1802AC, CDP1802BC Static Electrical Specifications at T PARAMETER SYMBOL Quiescent Device Current I DD Output Low Drive (Sink) Current I OL (Except XTAL) XTAL Output High Drive (Source) Current I OH (Except XTAL) XTAL Output Voltage Low Level V ...

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CDP1802A, CDP1802AC, CDP1802BC Static Electrical Specifications at T PARAMETER SYMBOL Input Capacitance C IN Output Capacitance C OUT NOTES Typical values are for T = +25 C and nominal Idle “00” at M(0000 ...

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CDP1802A, CDP1802AC, CDP1802BC Dynamic Electrical Specifications PARAMETER Clock to State Code Clock to Q Clock MINIMUM SET UP AND HOLD TIMES Data Bus Input Set Up Data Bus Input Hold DMA Set Up DMA Hold ...

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CDP1802A, CDP1802AC, CDP1802BC Dynamic Electrical Specifications PARAMETER EF1-4 Set Up EF1-4 Hold Minimum Pulse Width Times CLEAR Pulse Width CLOCK Pulse Width NOTES Typical values are for T = +25 C and nominal Maximum limits ...

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CDP1802A, CDP1802AC, CDP1802BC Timing Specifications as a function of T(T = 1/f PARAMETERS SYMBOL Required Memory Access Time Ad- t ACC dress to Data MRD to TPA t SU NOTE Typical values are for T = +25 C ...

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CDP1802A, CDP1802AC, CDP1802BC Timing Waveforms (Continued CLOCK PLH TPA TPB MEMORY PLH PHL HIGH ORDER ADDRESS ADDRESS BYTE MRD t t PLH PHL (MEMORY READ CYCLE) ...

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CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms CLOCK TPA TPB MACHINE CYCLE n CYCLE MA HIGH ADD LOW ADDRESS INSTRUCTION FETCH (S0) MEMORY READ CYCLE MRD MWR (HIGH) MEMORY OUTPUT ALLOWABLE MEMORY ACCESS “DON’T ...

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CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms INSTRUCTION FETCH (S0) MEMORY READ CYCLE MRD MWR (HIGH) MEMORY OUTPUT ALLOWABLE MEMORY ACCESS “DON’T CARE” OR INTERNAL DELAYS FIGURE 8. MEMORY READ CYCLE TIMING WAVEFORMS INSTRUCTION FETCH (S0) MEMORY READ CYCLE MRD ...

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CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms CLOCK TPA TPB MACHINE CYCLE n CYCLE INSTRUCTION FETCH (S0) MRD MWR MEMORY OUTPUT ALLOWABLE MEMORY ACCESS DATA BUS (NOTE 1) MEMORY READ CYCLE NOTE 1 ...

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CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms CLOCK TPA TPB MACHINE CYCLE n CYCLE INSTRUCTION FETCH (S0) DMA-IN MRD MWR MEMORY OUTPUT DATA BUS (NOTE 1) MEMORY READ CYCLE NOTE 1 USER GENERATED SIGNAL ...

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CDP1802A, CDP1802AC, CDP1802BC Machine Cycle Timing Waveforms CLOCK TPA TPB MACHINE CYCLE n CYCLE INSTRUCTION FETCH (S0) MRD MWR INTERRUPT (NOTE 1) (INTERNAL) IE MEMORY OUTPUT MEMORY READ CYCLE NOTE 1 USER GENERATED SIGNAL ...

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CDP1802A, CDP1802AC, CDP1802BC Performance Curves (Continued) 400 350 300 250 200 t 150 TLH 100 t THL 100 125 150 C , LOAD CAPACITANCE (pF) L ...

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CDP1802A, CDP1802AC, CDP1802BC Performance Curves (Continued - + GATE-TO-SOURCE = DRAIN-TO-SOURCE VOLTAGE (V) DS FIGURE 21. CDP1802BC MINIMUM OUTPUT ...

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CDP1802A, CDP1802AC, CDP1802BC INTERRUPT, DMA-lN, DMA-OUT (3 I/O Requests) These inputs are sampled by the CPU during the interval between the leading edge of TPB and the leading edge of TPA. Interrupt Action - X and P are stored in ...

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CDP1802A, CDP1802AC, CDP1802BC The three paths, depending on the nature of the instruction, may operate independently or in various combinations in the same machine cycle. With two exceptions, CPU instruction consists of two 8- clock-pulse machine cycles. The first cycle ...

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CDP1802A, CDP1802AC, CDP1802BC Interrupt Servicing Register R(1) is always used as the program counter when- ever interrupt servicing is initiated. When an interrupt request occurs and the interrupt is allowed by the program (again, nothing takes place until the completion ...

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CDP1802A, CDP1802AC, CDP1802BC loaded into D, and R(N) is incremented by 1. IDLE DMA INT S1 RESET S1 INIT DMA DMA S2 DMA DMA INT PRIORITY: FORCE S0, S1 DMA IN DMA OUT INT TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) ...

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CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) INSTRUCTION EXCLUSIVE OR EXCLUSIVE OR IMMEDIATE AND AND IMMEDIATE SHIFT RIGHT SHIFT RIGHT WITH CARRY RING SHIFT RIGHT SHIFT LEFT SHIFT LEFT WITH CARRY RING SHIFT LEFT ARITHMETIC OPERATIONS (Note ...

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CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) INSTRUCTION SHORT BRANCH IF EF1 = 1 (EF1 = SHORT BRANCH IF EF1 = 0 (EF1 = SHORT BRANCH IF EF2 = 1 (EF2 ...

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CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) INSTRUCTION RESET Q SAVE PUSH STACK RETURN DISABLE INPUT - OUTPUT BYTE TRANSFER OUTPUT 1 OUTPUT 2 OUTPUT 3 OUTPUT 4 OUTPUT 5 OUTPUT 6 OUTPUT 7 ...

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CDP1802A, CDP1802AC, CDP1802BC TABLE 1. INSTRUCTION SUMMARY (SEE NOTES) (Continued) INSTRUCTION NOTES: (For Table 1) 1. The arithmetic operations and the shift instructions are the only instructions that can alter the DF. After an add instruction denotes ...

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CDP1802A, CDP1802AC, CDP1802BC TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES STATE I N SYMBOL S1 RESET Initialize, Not Programmer 0000 Accessible S0 FETCH MRP S1 0 ...

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CDP1802A, CDP1802AC, CDP1802BC TABLE 2. CONDITIONS ON DATA BUS AND MEMORY ADDRESS LINES DURING ALL MACHINE STATES (Continued) STATE I N SYMBOL MARK ( REQ SEQ ...

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... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...