ADAU1592ASVZ-RL Analog Devices Inc, ADAU1592ASVZ-RL Datasheet - Page 19
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ADAU1592ASVZ-RL
Manufacturer Part Number
ADAU1592ASVZ-RL
Description
IC AMP AUDIO PWR 24W STER 48TQFP
Manufacturer
Analog Devices Inc
Type
Class Dr
Datasheet
1.ADAU1592ACPZ.pdf
(24 pages)
Specifications of ADAU1592ASVZ-RL
Output Type
2-Channel (Stereo)
Max Output Power X Channels @ Load
24W x 2 @ 4 Ohm
Voltage - Supply
9 V ~ 18 V
Features
Depop, Mute, Short-Circuit and Thermal Protection, Standby
Mounting Type
Surface Mount
Package / Case
48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
To shut down the power supplies to save power, it is highly
recommended to mute the amplifier before shutting down any
of the supplies. To achieve this, first pull down MUTE , then
shut down the power supplies in the following order: PVDD,
DVDD, and then AVDD. Where AVDD and DVDD are
generated from a single source, shut down PVDD before
shutting down DVDD and AVDD, and after issuing MUTE .
DC OFFSET AND POP NOISE
This section describes the cause of dc offset and pop noise
during turn-on/turn-off. The turn-on/turn-off pop in amplifiers
depends mainly on the dc offset, therefore, care must be taken
to reduce the dc offset at the output.
The first stage of the ADAU1592 has an inverting PGA amplifier,
as shown in Figure 48.
where:
R
R
setting).
R
C
C
V
V
As shown in Figure 48, the dc offset at the output can be due to
V
leakage current of the C
Normally, the offset due to leakage current in the C
can be ignored compared to V
ble for the dc offset at the output. The ADAU1592 uses special
self-calibration or a dc offset trim circuit, which controls the dc
offset (due to V
part as well as for voltage and temperature. The trim circuit
ensures that the offset is limited within specified limits and
provides virtually pop-free operation every time the part is
turned on. However, care must be taken while unmuting or
during the power-up sequence.
During the initial power-up, C
AVDD/2 and, during this time, there can be dc offset at the
output (see Figure 48). This depends on the PGA gain setting.
The dc offset is multiplied by the PGA gain setting. If the
amplifier is kept in mute during this charging and self-trimming
event for the recommended t
output remains within ±3 mV. For more details on t
the Power-Up/Power-Down Sequence section.
IN
FB
SOURCE
IN
REF
REF
MIS
MIS
= 20 kΩ, fixed internally.
is the gain feedback resistor (value depends on the PGA
is the input coupling capacitor (2.2 μF typical).
is the filter capacitor for V
is the analog reference voltage (AVDD/2 typical).
is the dc offset due to mismatch in the op amp.
(the dc offset from mismatch in the op amp) and due to
is the source resistance.
R
SOURCE
C
MIS
C
IN
REF
Figure 48. Input Equivalent Circuit
) to within ±3 mV. The V
AINx
V
REF
CHANGES WITH PGA SETTING
IN
R
capacitor.
IN
WAIT
MIS
V
IN
REF
MIS
. The V
and C
time, the dc offset at the
.
R
FB
REF
TO NEXT STAGE
MIS
are charging to
is mainly responsi-
MIS
can vary for each
IN
WAIT
is less and
, refer to
Rev. A | Page 19 of 24
The amount of pop at the turn-on depends on t
turn depends on the values of C
section describes how to select the value for the C
SELECTING VALUES FOR C
C
V
as well as the modulator. Therefore, care must be taken to ensure
that the recommended minimum value is used. The minimum
recommended value for C
C
inputs from the external dc. The C
corner frequency of the amplifier. It can be determined from
the following equation:
where:
f
R
C
Note that R
with respect to R
calculation.
From the preceding equation, f
frequency response.
The recommended value for C
and should keep 20 Hz roll-off within −0.5 dB.
However, if a higher than recommended C
better low frequency response, care must be taken to ensure that
appropriate t
Sequence section for more details.
MONO MODE
The ADAU1592 mono mode can be enabled by pulling MO/ ST
(Pin 11) to logic high. In this mode, the left channel input and
modulator are active and feed PWM data to both the left and
right power stages. However, the respective power FETs need to
be connected externally for higher current capability. That is,
connect OUTL+ with OUTR+ and OUTL− with OUTR−. The
mono mode gives the capability to drive lower impedance loads
without invoking current limit. However, the output power is
limited by PVDD and temperature limits. See the typical applica-
tion schematic in Figure 50 for details.
POWER SUPPLY DECOUPLING
Because Class-D amplifiers utilize high frequency switching,
care must be taken for power supply decoupling.
For reliable operation, using 100 nF ceramic surface-mount
capacitors for the PVDD and PGND pins is recommended. A
minimum of two capacitors is needed: one between Pin 45/Pin 46
(PVDD) and Pin 47/Pin48 (PGND), the other between Pin 39/
Pin 40 (PVDD) and Pin 37/Pin 38 (PGND). In addition, these
LOW
IN
IN
REF
IN
REF
is the input resistance (20 kΩ).
is the input coupling capacitor.
is the input coupling capacitor and is used to decouple the
. V
is the low corner frequency (−3 dB).
is the capacitor used for filtering the noise from AVDD on
f
LOW
REF
is used for the biasing of the internal analog amplifier
=
IN
WAIT
2
= 20 kΩ and R
×
π
IN
is used. See the Power-Up/Power-Down
×
, it also must be taken into account in
R
1
IN
×
C
REF
IN
SOURCE
is 4.7 μF.
IN
LOW
REF
is 2.2 μF, giving f
REF
< 1 kΩ. If R
IN
and C
can be found for the desired
value determines the low
AND C
IN
. The following
IN
value is used for
IN
SOURCE
WAIT
ADAU1592
LOW
REF
, which in
is sizable
and C
= 3.6 Hz,
IN
.