HFA3860BIV Intersil Corporation, HFA3860BIV Datasheet
HFA3860BIV
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HFA3860BIV Summary of contents
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... The HFA3860B is housed in a thin plastic quad flat package (TQFP) suitable for PCMCIA board applications. Ordering Information TEMP. o PART NO. RANGE ( C) PKG. TYPE HFA3860BIV - TQFP HFA3860BIV96 - Tape and Reel Pinout HFA3860B (TQFP ...
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Table of Contents Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Typical Application Diagram HFA3424 (NOTE) (FILE# 4131) HFA3624 UP/DOWN CONVERTER (FILE# 4066) RFPA HFA3925 (FILE# 4132) HFA3524 TYPICAL TRANSCEIVER APPLICATION CIRCUIT USING THE HFA3860B NOTE: Required for systems targeting 802.11 specifications. For additional information on the PRISM™ chip set, call ...
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Pin Descriptions (Continued) NAME PIN TYPE I/O TX_PE 2 I TXD 3 I TXCLK 4 O TX_RDY 5 O CCA 32 O RXD 35 O RXCLK 36 O MD_RDY 34 O RX_PE I/O SCLK 24 I ...
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Pin Descriptions (Continued) NAME PIN TYPE I/O TEST_CK 1 O RESET 28 I MCLK OUT OUT NOTE: Total of 48 pins; ALL pins are used. External Interfaces There are three primary digital ...
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SCLK 7 SD MSB R/W CS NOTES: 1. The HFA3860B always uses the rising edge of SCLK. SD, R/W and CS hold times allow the controller to use either the rising or falling edge. 2. This port operates essentially ...
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TABLE 1. CONFIGURATION AND CONTROL INTERNAL REGISTER LIST (Continued) CONFIGURATION REGISTER CR16 (Note 3) CR17 (Note 3) CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30 CR31 NOTE provide CCK functionality, these registers must ...
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TXCLK TX_PE TXD TX_RDY NOTE: Preamble/Header and Data is transmitted LSB first. TXD shown generated from rising edge of TXCLK. RXCLK RX_PE HEADER FIELDS PROCESSING PREAMBLE/HEADER MD_RDY RXD NOTE: MD_RDY active after CRC16. See detailed timing diagrams (see Figures 22, ...
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TABLE A/D SPECIFICATIONS PARAMETER MIN Full Scale Input Voltage (V ) 0.25 P-P Input Bandwidth (-0.5dB) - Input Capacitance (pF) - Input Impedance (DC (Sampling Frequency) - The voltages applied to pin 16, V REFP ...
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A/D_CK RX_I_IN A RX_Q_IN A A/D_CAL_POS A/D_CAL_NEG V REFN ANALOG BIASES D/A V REFP RSSI A/D Interface The Receive Signal Strength Indication (RSSI) analog signal is input to a 6-bit A/D, indicating 64 discrete levels of ...
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TABLE 5. TEST MODES (Continued) MODE DESCRIPTION TEST_CLK 11 Reserved Reserved 12 A/D Cal Test A/D Cal CLK Mode 13 Correlator I High Sample CLK Rate 14 Correlator Q Sample CLK High Rate 15 Chip Error 0 Accumulator 16 NCO ...
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Power Down Modes The power consumption modes of the HFA3860B are controlled by the following control signals. Receiver Power Enable (RX_PE, pin 33), which disables the receiver when inactive. Transmitter Power Enable (TX_PE, pin 2), which disables the transmitter when ...
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TABLE 7. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz DATA A/D SAMPLE CLOCK MODULATION (MHz) DBPSK 22 DQPSK 22 BMBOK/CCK 22 QMBOK/CCK 22 802.11 DSSS BPSK 802.11 DSSS QPSK 1 MB/S 2 MB/S BARKER BARKER DATA 1 BIT ENCODED ...
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PREAMBLE (SYNC) SFD 128 BITS 16 BITS PREAMBLE Service Field (8 Bits) - This field has one bit that is used to supplement the length field and the rest are currently unassigned and can be utilized as required by the ...
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Scrambling is done by a polynomial division using a prescribed polynomial as shown in Figure 10. A shift register holds the last quotient and the output is the exclusive-or of the data and the sum of taps in the shift ...
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DIBIT PATTERN (D(0), D(1)) D(0) IS FIRST IN TIME CCK Modulation The spreading code length is 8 and based on complementary codes. The chipping rate is 11 Mchip/s. The symbol duration is exactly 8 complex chips ...
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Clear Channel Assessment (CCA) and Energy Detect (ED) Description The clear channel assessment (CCA) circuit implements the carrier sense portion of a carrier sense multiple access (CSMA) networking scheme. The Clear Channel Assessment (CCA) monitors the environment to determine when ...
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Demodulator Description The receiver portion of the baseband processor, performs A/D conversion and demodulation of the spread spectrum signal. It correlates the PN spread symbols, then demodulates the DBPSK, DQPSK, BMBOK, QMBOK, or CCK symbols. The demodulator includes a frequency ...
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After a brief setup time as illustrated on the timeline of Figure 12, the signal begins to emerge from the demodulator. It takes 7 more symbols to seed the descrambler before valid data is available. This occurs in time for ...
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V (ANALOG) DD (10, 18, 20) HIGH RATE (MBOK/CCK) MODULATOR I (12 (13 (16) REFP V (17) REFN B/Q MUX RSSI (14) ANTSEL (26) ANTSEL (27) I (48) OUT XOR Q (47) OUT XOR 11-BIT PN ...
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TX POWER RAMP 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS 16 SYMBOLS JUST NO MISSED SIG DET FOUND ANT1 ANT2 NOTES: 4. Worst Case Timing; antenna dwell starts before signal is full ...
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SAMPLES AT 2X CHIP RATE CORRELATION TIME T0 CORRELATOR OUTPUT IS THE RESULT OF CORRELATING THE PN SEQUENCE WITH THE RECEIVED SIGNAL These correlators are time invariant matched filters otherwise known as parallel correlators. They use one sample per chip ...
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When a symbol error is made usually a single bit error even in QPSK mode. When a symbol is in error, the next symbol will also be decoded wrong since the ...
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V (ANALOG) DD (10, 18, 20) VR3+ 3-BIT I (12) IN A/D 3 3-BIT Q (13) IN A/D 3 REF 2V VR3- V (16) REFP 1.75V A/D REF (MAX) AND V (17) LEVEL ADJ. REFN 0.25V (MIN) RSSI REF 6-BIT ...
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Tracking Chip tracking is performed on the de-rotated signal samples from the complex multiplier. These are alternately routed into two streams. The END chip samples are the same as those used for the correlators. The MID chip samples should lie ...
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BER 1.0 BER 2.0 BER 5.5 BER 11 -06 1.00E -50 -40 -30 -20 - CLOCK OFFSET (PPM) FIGURE 18. BER vs CLOCK OFFSET -04 1.00E -05 1.00E BER 1.0 BER 2.0 BER 5.5 ...
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A Default Register Configuration The registers in the HFA3860B are addressed with 6-bit numbers where the lower 2 bits of an 8-bit hexadecimal address are left as unused. This results in the addresses being in increments shown ...
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Control Registers The following tables describe the function of each control register along with the associated bits in each control register. CONFIGURATION REGISTER 0 ADDRESS (0h) PART/VERSION CODE Bit 7:4 Part Code 0 = HFA3860 series Bit 3:0 Version Code ...
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CONFIGURATION REGISTER 2 ADDRESS (08h) TX AND RX CONTROL (Continued) Write to control, Read to verify control, setup while TX_PE and RX_PE are low Bit 1 MD_RDY Start. Sets where MD_RDY will become active After SFD detect (normal). ...
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CONFIGURATION REGISTER 7 ADDRESS (1Ch) SCRAMBLER TAPS (Continued) Bits 6:0 This register is used to configure the transmit scrambler with a 7-bit polynomial tap configuration. The transmit scrambler is a 7-bit shift register, with 7 configurable taps. A logic 1 ...
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CONFIGURATION REGISTER 16 ADDRESS (40h) SIGNAL FIELD DBPSK/ CCK QCOVER Bits 7:0 This register contains an 8-bit value defining the data packet modulation as DBPSK. This value will be a 0Ah for 802.11, and is used in the transmitted Signalling ...
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CONFIGURATION REGISTER 24 ADDRESS (60h) RX STATUS This read only register is provided for MACs that can’t process the header fields from the RXD port. Bit 4 SFD search status (set to 0 when RX_PE is inactive Searching ...
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CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS (Continued) Supplies address for test pin outputs and Test Bus Monitor Register Bits 7:0 Test Bus Address = 03h RSSI Monitor Test 7 = CSE Enhanced. Used in enhanced CCA dual antenna ...
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CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS (Continued) Supplies address for test pin outputs and Test Bus Monitor Register Bits 7:0 Test Bus Address = 10h NCO Test Hi Rate, tests the NCO in the high rate tracking section. ...
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CONFIGURATION REGISTER 28 ADDRESS (70h) TEST BUS ADDRESS (Continued) Supplies address for test pin outputs and Test Bus Monitor Register Bits 7:0 Test Bus Address = 1Eh to 1Fh Reserved Test 7:0 + TestCLK = 0 CONFIGURATION REGISTER 29 ADDRESS ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications V = 3.0V to 3.3V 10 PARAMETER TXD Modulation Extension RX_PE Inactive Width RX_CLK Period (11Mbps Mode) RX_CLK Width Hi or Low (11Mbps Mode) RX_CLK to RXD MD_RDY to 1st RX_CLK RXD to 1st RX_CLK Setup ...
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I and Q A/D AC Electrical Specifications PARAMETER Full Scale Input Voltage (V ) P-P Input Bandwidth (-0.5dB) Input Capacitance Input Impedance (DC) FS (Sampling Frequency) RSSI A/D Electrical Specifications PARAMETER Full Scale Input Voltage (V ) P-P Input Bandwidth ...
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TX_PE OUT OUT TXRDY TX_CLK TXD t RLP RX_PE MD_RDY RX_CLK RXD CCA, RSSI NOTE: RXD, MD_RDY is output two MCLK after RXCLK rising to provide hold time. RSSI Output ...
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