HT46R23 Holtek, HT46R23 Datasheet
HT46R23
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HT46R23 Summary of contents
Page 1
... A HALT feature is included to reduce power con- sumption trademark of Philips Semiconductors. Rev. 1.30 HT46R23 8-Bit OTP Microcontroller Up to 0.5 s instruction cycle with 8MHz system clock at V =5V DD 8-level subroutine nesting 8 channels 10-bit resolution (9-bit accuracy) A/D con- ...
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... Block Diagram Pin Assignment Rev. 1.30 HT46R23 2 August 17, 2001 ...
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... Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.30 Description 2 C BUS function is used, the in- +5.5V Storage Temperature ............................ 125 C SS +0.3V Operating Temperature........................... HT46R23 August 17, 2001 ...
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... 0.9V 3. 0.9V DD 2.7 3.3V V =0. =0. 3.3V V =0. =0. 3. 0.5 4 HT46R23 Ta=25 C Max. Unit 5 ...
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... Power-up, reset or 1024 wake-up from HALT 1 Connect to external 64 pull-high resistor 2k 5 HT46R23 Ta=25 C Max. Unit 4000 kHz 8000 kHz 4000 kHz 8000 kHz 4000 kHz 8000 kHz 168 s 144 SYS s *t SYS ...
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... PC S10 Program counter S11~S0: Stack register bits @7~@0: PCL bits 6 HT46R23 * ...
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... These areas may function as normal program memory depending upon the requirements. Table Location * Table location P11~P8: Current program counter bits 7 HT46R23 C BUS interrupt service * August 17, 2001 ...
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... All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by SET [m].i and CLR [m].i . They are also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). 8 HT46R23 August 17, 2001 ...
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... SP is decremented. If immediate service is desired, the stack must be pre- vented from becoming full. All these kinds of interrupts have a wake-up capability interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by Function Status register 9 HT46R23 August 17, 2001 ...
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... Unused bit, read as 0 (1EH BUS interrupt request 4 HIF flag (1= active; 0= inactive) 5 Unused bit, read BUS 6 Unused bit, read Unused bit, read as 0 INTC1 register 10 HT46R23 Priority Vector 1 04H 2 08H 3 0CH 4 10H Function 2 C BUS inter- August 17, 2001 ...
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... PC and SP are reset to zero. To clear the contents of WDT, three methods are adopted; external reset (a low level to RES), software instructions HALT instruction. The software instructions include CLR WDT and the other set Watchdog Timer 11 HT46R23 the maxi- 15 ...
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... Most registers are reset to the initial condition when the reset condi- tions are met. By examining the PD and TO flags, the program can distinguish between different chip resets . Reset timing chart Reset circuit (sys- SYS Reset configuration 12 HT46R23 August 17, 2001 ...
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... August 17, 2001 HT46R23 (HALT)* uuuu uuuu uuuu uuuu uu-u uuuu 000H uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu --11 uuuu -uuu uuuu ---u ---u ...
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... To enable the counting operation, the timer ON bit (TON; bit 4 of TMRC) should be set the pulse width measurement mode, the TON will be cleared au- tomatically after the measurement cycle is completed. Timer/Event Counter 14 HT46R23 WDT Time-out (HALT)* uu-- ---- uuuu uuuu uuuu uuuu u--- --uu ...
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... PFD output signal is controlled by PA3 data register only. The I/O functions of PA3 are shown below. I/O I/P O/P I/P Mode (Normal) (Normal) (PFD) Logical Logical Logical PA3 Input Output Input Note: The PFD frequency is the timer/event counter overflow frequency dividedby 2. 15 August 17, 2001 HT46R23 O/P (PFD) PFD (Timer on) ...
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... In a (7+1) bits PWM function, the contents of the PWM . register is divided into two groups. Group 1 of the PWM SYS register is denoted by DC which is the value of PWM.7~PWM.1. The group 2 is denoted by AC which is the value of PWM.0. 16 HT46R23 Duty Cycle DC 1 i< ...
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... The bit5~bit3 of the ADCR are used to set PB configurations. PB can be an analog input or as digital I/O line decided by these 3 bits. Once a PB line is selected as an analog input, the I/O functions and pull-high resistor of this I/O line are disabled and the A/D 17 HT46R23 August 17, 2001 ...
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... PB5 PB4 PB3 PB2 PB6 PB5 PB4 PB3 A2 PB6 PB5 PB4 A3 A2 PB6 PB5 PB6 Port B configuration 18 HT46R23 Analog Channel PB1 PB0 PB1 ...
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... Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 1.30 A/D conversion timing The relationship between V and V DD Note the voltage range for proper chip OPR operation at 4MHz system clock. Low voltage reset 19 HT46R23 is shown below. LVR August 17, 2001 ...
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... Unused bit, read define the transmit/receive mode HTX 4 (0= receive mode; 1= transmit) To enable/disable transmit acknowledge TXAK 3 (0= acknowledge; 1= don t acknowledge BUS, 0~2 Unused bit, read as 0 HCR register 20 HT46R23 2 C BUS receives a Bit0 2 C BUS, the Function 2 C BUS function August 17, 2001 ...
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... I C BUS. The slave device check this bit to understand itself transmitter or a receiver. The SRW bit is set to 1 means that the mas- 2 ter wants to read data from the I C BUS, so the slave de- Slave address 21 HT46R23 August 17, 2001 ...
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... I change to receive mode and dummy read the HDR reg- ister to release the SDA line and the master sends the STOP signal. Stop bit Start bit 2 C BUS. Data stable and data allow change 22 HT46R23 2 C BUS or August 17, 2001 ...
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... Rev. 1.30 23 August 17, 2001 HT46R23 ...
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... Rev. 1.30 24 August 17, 2001 HT46R23 ...
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... ROM code option The following shows ten kinds of ROM code option in the HT46R23. ALL the ROM code options must be defined to en- sure proper system function. No. 1 OSC type selection. This option is to decide crystal oscillator is chosen as system clock. WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable the 2 WDT ...
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... Application Circuits Rev. 1. August 17, 2001 HT46R23 ...
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... Rotate data memory left through carry Data Move MOV A,[m] Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.30 Instruction Description 27 HT46R23 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 Z,C,AC,OV 1 Z,C,AC,OV (1) 1 Z,C,AC,OV 1 ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO is set and the PD is cleared. Otherwise the TO and PD flags remain unchanged. Rev. 1.30 Instruction Description 28 HT46R23 Flag Cycle Affected 2 None (2) 1 None ...
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... Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... Affected flag(s) TC2 TC1 TO CLR [m] Clear data memory. Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TC2 TC1 TO Rev. 1. 00H 00H 00H HT46R23 August 17, 2001 ...
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... Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TC2 TC1 TO Rev. 1. (ACC.3~ACC.0), AC1 HT46R23 August 17, 2001 ...
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... TC1 TO MOV A,[m] Move data memory to the accumulator. Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... Data in the data memory (one of the data memory) and the accumulator perform a bitwise log- ical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the ro- tated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TC2 TC1 TO Rev HT46R23 August 17, 2001 ...
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... Oth- erwise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TC2 TC1 TO Rev. 1. ([m]+ ([m]+ HT46R23 August 17, 2001 ...
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... The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0 Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH code (high byte) Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR opera- tion. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TC2 TC1 TO Rev. 1. HT46R23 August 17, 2001 ...
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... Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.30 42 August 17, 2001 HT46R23 ...