CY7C1350-133AC Cypress Semiconductor Corporation., CY7C1350-133AC Datasheet
CY7C1350-133AC
Related parts for CY7C1350-133AC
CY7C1350-133AC Summary of contents
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... The CY7C1350 is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350 is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle ...
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... DDQ DDQ 100-Pin TQFP CY7C1350 2 CY7C1350 DDQ DDQ ...
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... When left floating MODE will default HIGH inter- leaved burst order. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. 3 CY7C1350 controls DQ and DP , BWS 0 [7:0] ...
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... Read/Modify/Write sequences, which can be reduced to sim- ple byte write operations. Because the CY7C1350 is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before present- ing data to the DQ three-state the output drivers ...
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... Burst Write Accesses The CY7C1350 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial ad- dress, as described in the Single Write Access section above. ...
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... BWS . Bytes not selected during byte writes remain unaltered. All x [3:0] 6 CY7C1350 BWS BWS BWS ...
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... V > V – 0.3V DDQ , Device Deselected, or 7.0-ns cycle, 143 MHz DD 0. > V – 0. DDQ 7.5-ns cycle, 133 MHz = 1/t MAX CYC 10.0-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz 7 CY7C1350 Ambient [10] Temperature DDQ 0°C to +70°C 3.3V ± 5% Min. Max. 3.135 3.465 3.135 3.465 2.4 0.4 2.0 V 0.3V DD ...
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... AC Test Loads. Test Conditions T = 25° MHz 3.3V 3.3V DDQ R=317 3.3V OUTPUT 5 pF R=351 GND INCLUDING JIG AND SCOPE 1350-2 (b) Test Conditions Symbol 8 CY7C1350 Max. Unit [13] ALL INPUT PULSES 3.0V TQFP Typ. Units Notes ...
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... This parameter is sampled and not 100% tested. [13, 14, 15] -143 Min. Max. Min. 7.0 7.5 2.0 3.0 2.0 3.0 2.0 2.0 0.5 0.5 4.0 1.5 1.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 2.0 2.0 0.5 0.5 1.7 1.7 0.5 0.5 2.0 2.0 0.5 0.5 1.5 3.5 1.5 1.5 1.5 [12, 14, 15, 16] 4.0 [12, 14, 15, 16 4.0 is less than t and t is less than t to eliminate bus contention between SRAMs when sharing the same EOLZ CHZ CLZ 9 CY7C1350 -133 -100 -80 Max. Min. Max. Min. Max. 10 12.5 4.0 4.0 4.0 4.0 2.2 2.5 0.5 1.0 4.2 5.0 7.0 1.5 1.5 2.2 2.5 0.5 1.0 2.2 2.5 0.5 1.0 2.2 2.5 0.5 1.0 2.0 2.5 0.5 1.0 2.2 2.5 0.5 1.0 3.5 1.5 3.5 1.5 5.0 1.5 1.5 4.2 5.0 7 4.2 5.0 7 ...
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... Q3 In Out Out define a write cycle (see Write Cycle Description table). [3: and CE . All chip enables need to be active in order to select DON’T CARE = UNDEFINED 10 CY7C1350 t t CENH CENS CEN HIGH blocks all synchronous inputs RA7 t CHZ Out Out ...
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... AH AS WA2 CHZ Q1+2 Q1+3 Q1+1 Out Out Out define a write cycle (see Write Cycle Description table). [3: and CE . All chip enables need to be active in order to select UNDEFINED = DON’T CARE 11 CY7C1350 RA3 t CLZ D2+2 D2+3 D2 input signals. [3:0] Q3 Out ...
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... Switching Waveforms (continued) OE Timing Ordering Information Speed (MHz) Ordering Code 143 CY7C1350-143AC 133 CY7C1350-133AC 100 CY7C1350-100AC 80 CY7C1350-80AC Document #: 38 00690– EOHZ Three-state I/O’s t EOLZ Package Name Package Type A101 100-Lead ( 1.4 mm) Thin Quad Flat Pack A101 100-Lead ( 1.4 mm) Thin Quad Flat Pack A101 100-Lead ( ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1350 51-85050-A ...