CY7C185-20SC Cypress Semiconductor Corporation., CY7C185-20SC Datasheet

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CY7C185-20SC

Manufacturer Part Number
CY7C185-20SC
Description
8Kx8 Static RAM
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Features
Functional Description
The CY7C185 is a high-performance CMOS static RAM orga-
nized as 8192 words by 8 bits. Easy memory expansion is
Selection Guide
Cypress Semiconductor Corporation
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Note:
• High speed
• Fast t
• Low active power
• Low standby power
• CMOS for optimum speed/power
• Easy memory expansion with CE
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
1.
Logic Block Diagram
— 15 ns
— 715 mW
— 220 mW
For military specifications, see the CY7C185A datasheet.
CE
CE
WE
OE
1
2
DOE
A
A
A
A
A
A
A
A
1
2
3
4
5
6
7
8
[1]
COLUMN DECODER
INPUT BUFFER
256 x 32 x 8
ARRAY
1
, CE
2
, and OE features
3901 North First Street
POWER
DOWN
7C185–15
40/15
130
15
provided by an active LOW chip enable (CE
chip enable (CE
three-state drivers. This device has an automatic power-down
feature (CE
when deselected. The CY7C185 is in a standard 300-mil-wide
DIP, SOJ, or SOIC package.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE
puts are both LOW and CE
input/output pins (I/O
location addressed by the address present on the address
pins (A
selecting the device and enabling the outputs, CE
active LOW, CE
HIGH. Under these conditions, the contents of the location ad-
dressed by the information on address pins are present on the
eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to insure alpha immunity.
7C185–20
0
20/15
through A
C185–1
110
20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1
San Jose
or CE
0
1
2
3
4
5
6
7
2
2
), and active LOW output enable (OE) and
active HIGH, while WE remains inactive or
2
12
), reducing the power consumption by 70%
). Reading the device is accomplished by
0
through I/O
8K x 8 Static RAM
7C185–25
2
20/15
100
CA 95134
is HIGH, data on the eight data
25
Pin Configurations
GND
I/O
I/O
I/O
A
A
A
NC
A
A
A
A
A
A
10
11
12
7
4
5
6
7
8
9
0
1
2
) is written into the memory
DIP/SOJ/SOIC
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
), an active HIGH
CY7C185
August 12, 1998
fax id: 1013
7C185–35
408-943-2600
V
WE
CE
A
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
1
20/15
CC
3
2
1
0
100
and WE in-
7
6
5
4
3
2
1
35
1
C185–2
and OE

Related parts for CY7C185-20SC

CY7C185-20SC Summary of contents

Page 1

... CMOS for optimum speed/power • Easy memory expansion with • TTL-compatible inputs and outputs • Automatic power-down when deselected Functional Description The CY7C185 is a high-performance CMOS static RAM orga- nized as 8192 words by 8 bits. Easy memory expansion is Logic Block Diagram INPUT BUFFER ...

Page 2

... Max Min. Duty Cycle=100% Max – 0.3V 0. – CY7C185 Ambient Temperature + 10% – + 10% 7C185–15 7C185–20 Min. Max. Min. Max. Unit 2.4 2.4 V 0.4 0 2.2 V ...

Page 3

... 0. – Test Conditions MHz 5. 481 5V 3. GND 255 JIGAND SCOPE C185–4 (b) 1.73V 3 CY7C185 7C185–25 7C185-35 Min. Max. Min. Max. 2.4 2.4 0.4 0 0.3V 0.3V –0.5 0.8 –0.5 0.8 –5 +5 –5 +5 –5 +5 –5 +5 –300 – ...

Page 4

... AC Test Loads. Transition is measured 500 mV from steady state voltage less than t and t for any given device. HZCE LZCE1 LZCE2 LOW, CE HIGH, and WE LOW. All 3 signals must be active to initiate a write and either CY7C185 7C185–25 7C185–35 Max. Min. Max. Min. Max ...

Page 5

... LOW, CE HIGH and WE LOW going HIGH or CE going LOW. The data input set-up and hold timing should be referenced to the CY7C185 DATA VALID C185–6 t HZOE t HZCE HIGH IMPEDANCE t PD ICC 50% ISB C185– ...

Page 6

... LOW simultaneously with WE HIGH, the output remains in a high-impedance state SCE1 SCE2 DATA VALID IN [12,13,14,15 SCE1 t SCE2 DATA IN HZWE 6 CY7C185 VALID t LZWE and C185–9 C185–10 ...

Page 7

... AMBIENT TEMPERATURE ( C) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4. = 5.0 0.0 0 200 400 600 800 1000 CAPACITANCE (pF) 7 CY7C185 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. = 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 ...

Page 8

... CY7C185–15VC CY7C185–15VI 20 CY7C185–20PC CY7C185–20SC CY7C185–20VC CY7C185–20VI 25 CY7C185–25PC CY7C185–25SC CY7C185–25VC CY7C185–25VI 35 CY7C185–35PC CY7C185–35SC CY7C185–35VC CY7C185–35VI Document #: 38–00037–K Mode Deselect/Power-Down Deselect/Power-Down Read Write Deselect Name Package Type P21 ...

Page 9

... Package Diagrams 28-Lead (300-Mil) Molded DIP P21 28-Lead (300-Mil) Molded SOIC S21 9 CY7C185 51-85014-B 51-85026-A ...

Page 10

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 28-Lead (300-Mil) Molded SOJ V21 CY7C185 51-85031-B ...

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