MT90823AL Mitel, MT90823AL Datasheet

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MT90823AL

Manufacturer Part Number
MT90823AL
Description
3.0V; large digital switch. For medium and large switching platforms
Manufacturer
Mitel
Datasheet

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Part Number:
MT90823AL1
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Applications
Features
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
STi8
STi9
STi10
STi11
STi12
STi13
STi14
STi15
2,048
at 8.192 Mb/s
Per-channel variable or constant throughput
delay
Automatic identification of ST-BUS/GCI
interfaces
Accept ST-BUS streams of 2.048, 4.096 or
8.192 Mb/s
Automatic frame offset delay measurement
Per-stream frame delay offset programming
Per-channel high impedance output control
Per-channel message mode
Control interface compatible to Motorola
non-multiplexed CPUs
Connection memory block programming
3.3V local I/O with 5V tolerant inputs and
TTL-compatible outputs
IEEE-1149.1 (JTAG) Test Port
Medium and large switching platforms
CTI application
Voice/data multiplexer
Digital cross connects
ST-BUS/GCI interface functions
Support IEEE 802.9a standard
2,048 channel non-blocking switching
V
DD
CLK
Converter
Parallel
Serial
V
to
SS
F0i
Timing
Unit
HCLK
FE/
WFPS
TMS
Figure 1 - Functional Block Diagram
ALE
AS/ IM DS/
TDI
Multiple Buffer
Data Memory
Microprocessor Interface
TDO
Registers
Internal
RD
Loopback
Test Port
CS R/W
TCK TRST
/WR
DS5064
Description
The
non-blocking switch capacity of: 2,048 x 2,048
channels at a serial bit rate of 8.192 Mb/s; 1,024 x
1,024 channels at 4.096 Mb/s; and 512 x 512
channels at 2.048 Mb/s. The device has many
features that are programmable on a per stream or
per channel basis, including message mode, input
offset delay and high impedance output control.
Per stream input delay control is particularly useful
for managing large multi-chip switches that transport
both voice channel and concatenated data channels.
In addition, the input stream can be individually
calibrated for input frame offset using a dedicated
pin.
A7-A0
MT90823
IC
Connection
Output
MUX
Memory
DTA D15-D8/
MT90823AP
MT90823AL
MT90823AB
MT90823AG
RESET
AD7-AD0
Ordering Information
Large
3V Large Digital Switch
-40 to +85 C
CSTo
ISSUE 3
Converter
Parallel
Serial
ODE
Digital
to
100 Pin MQFP
100 Pin LQFP
120 Pin PBGA
84 Pin PLCC
Switch
MT90823
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
STo8
STo9
STo10
STo11
STo12
STo13
STo14
STo15
January 2000
has
a
1

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MT90823AL Summary of contents

Page 1

... Microprocessor Interface WFPS AS/ IM DS/ CS R/W A7-A0 ALE RD /WR Figure 1 - Functional Block Diagram MT90823 3V Large Digital Switch ISSUE 3 Ordering Information MT90823AP 84 Pin PLCC MT90823AL 100 Pin MQFP MT90823AB 100 Pin LQFP MT90823AG 120 Pin PBGA -40 to +85 C MT90823 Large Digital Switch IC RESET ODE Parallel ...

Page 2

MT90823 CMOS STi0 STi1 STi2 STi3 STi4 STi5 STi6 STi7 STi8 STi9 STi10 STi11 STi12 STi13 STi14 STi15 F0i FE/HCLK VSS CLK VDD 80 78 STi0 STi1 82 STi2 STi3 84 STi4 86 STi5 STi6 88 STi7 STi8 90 STi9 ...

Page 3

A VSS VSS STo14 STo12 STo10 B VSS VSS STo15 STo13 STo11 C STi0 STi1 VSS VDD VSS D STi2 STi3 VDD E STi4 STi5 VSS F STi6 STi7 VDD G STi8 STi9 VSS ...

Page 4

MT90823 CMOS Pin Description Pin # 84 100 100 PLCC MQFP LQFP 1, 11, 31, 41, 28, A1,A2,A12,A13, 30, 54 56, 66, 38, B1,B2,B7,B12, 64, 75 76, 99 53, B13,C3,C5,C7, 63, C9,C11,E3,E11 73, G3,G11,J3,J11, 96 L3,L5,L7,L9,L11, M2,M12,M13,N1 2, 32, 5, ...

Page 5

Pin Description (continued) Pin # 84 100 100 PLCC MQFP LQFP 14- N6,M7,N7,N8 M8,N9,M9,N10 ...

Page 6

MT90823 CMOS Pin Description (continued) Pin # 84 100 100 PLCC MQFP LQFP 32- L12,L13,K12 K13,J12,J13, H12,H13 65 - 42- G12,G13,F12 ...

Page 7

... Mbit/s and are arranged in 125 s wide frames, which contain 32 128 channels, respectively. The data rates on input and output streams are identical. By using Mitel’s message mode capability, the microprocessor can access time-slots on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS devices ...

Page 8

MT90823 CMOS streams. For details on the use of the source address data (CAB and SAB bits), see Table 13 and Table 14. Once the source address bits are programmed by the microprocessor, the contents of the data memory at ...

Page 9

CLK of 8.192 MHz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels. 8.192 Mb/s Serial Links (DR0=0, DR1=1) When the 8.192 Mb/s data rate is selected, the device is configured with 16-input/16-output data streams ...

Page 10

MT90823 CMOS delay to ensure minimum delay between input and output data. In wideband data applications, select constant throughput delay to maintain the frame integrity of the information through the switch. The delay through the device varies according to the ...

Page 11

For multiplexed operation, the 8-bit data and address (AD0-AD7), 8-bit Data (D8-D15), Address strobe/ Address latch enable (AS/ALE), Data strobe/Read (DS/RD), Read/Write /Write (R/W / WR), Chip select (CS) and Data transfer acknowledge (DTA) signals are required. See Figure 13 ...

Page 12

MT90823 CMOS Bit V/C (Variable/Constant Delay) of each connection memory location allows the per-channel selection between variable and constant throughput delay modes. The loopback bit should be used for diagnostic purpose only; this bit should be set to zero for ...

Page 13

Initialization of the MT90823 During power up, the TRST pin should be pulsed low, or held low continuously, to ensure that the MT90863 is in the normal functional mode pull-down resistor can be connected to this pin so ...

Page 14

MT90823 CMOS Read/Write Address: Reset Value Bit Name 15-10 Unused Must be zero for normal operation. 9-5 BPD4-0 Block Programming Data. These bits carry the value to be loaded into the connection ...

Page 15

Read Address: Reset Value CFE FD11 0 Bit Name Unused Must be zero for normal operation. 12 CFE Complete Frame Evaluation. When CFE = 1, the frame evaluation is completed ...

Page 16

MT90823 CMOS Read/Write Address: Reset value OF32 OF31 OF30 DLE3 OF22 OF72 OF71 OF70 DLE7 OF62 OF112 OF111 OF110 DLE11 OF102 ...

Page 17

Input Stream Offset No clock period shift (Default) + 0.5 clock period shift +1.0 clock period shift +1.5 clock period shift +2.0 clock period shift +2.5 clock period shift +3.0 clock period shift +3.5 clock period shift +4.0 clock period ...

Page 18

MT90823 CMOS V/C MC CSTo LPBK Bit Name 15 LPBK 14 V CSTo SAB3-0 7 (Note CAB6-0 (Note 1) Note 1: If bit 13 ...

Page 19

JTAG Support The MT90823 JTAG interface conforms to the IEEE 1149.1 Boundary-Scan standard Boundary-Scan Test (BST) technique it specifies. The boundary-scan circuitry is controlled by an external test access port (TAP) Controller. Test Access Port (TAP) The Test Access Port ...

Page 20

MT90823 CMOS Boundary Scan Bit 0 to Bit 117 Device Pin Output Tristate Control STo7 0 STo6 2 STo5 4 STo4 6 STo3 8 STo2 10 STo1 12 STo0 14 ODE CSTo 17 DTA D15 20 D14 23 D13 26 ...

Page 21

Applications Switch Matrix Architectures The MT90823 is an ideal device for medium to large size switch matrices where voice and grouped data channels are transported within the same frame. In such applications, the voice samples have to be time interchanged ...

Page 22

MT90823 CMOS Wide Frame Pulse (WFP) Frame Alignment Mode When the device is in the wide frame pulse mode and if the input data streams are sampled at 3/4 bit time, the device can operate in the HMVIP and MVIP-90 ...

Page 23

Streams 4,096 x 4,096 Switch Matrix (Figure 6) IN 4,096 x 4,096 32 Streams Switch Matrix (Figure 6) Figure 9 - 8,192 x 8,192 Channel Switch Matrix DSTo E1 E1/T1 Trunk 0 DSTi 0 DSTo E1 E1/T1 Trunk 1 ...

Page 24

MT90823 CMOS Absolute Maximum Ratings* Parameter 1 Supply Voltage 2 Voltage on any 3.3V Tolerant pin I/O (other than supply pins) 3 Voltage on any 5V Tolerant pin I/O (other than supply pins) 4 Continuous Current at digital outputs 5 ...

Page 25

AC Electrical Characteristics - Frame Pulse and CLK Characteristic 1 Frame pulse width (ST-BUS, GCI) Bit rate = 2.048 Mb/s Bit rate = 4.096 Mb/s Bit rate = 8.192 Mb/s 2 Frame Pulse Setup time before CLK falling (ST-BUS or ...

Page 26

MT90823 CMOS AC Electrical Characteristics - Serial Streams for ST-BUS and GCI Backplanes Characteristic 1 Sti Set-up Time 2 Sti Hold Time 3 Sto Delay - Active to Active 4 STo delay - Active to High-Z 5 Sto delay - ...

Page 27

F0i CLK STo Bit 7, Last Ch (Note1) STi Bit 7, Last Ch (Note1) Note 1: 2Mb/s mode, last channel = ch 31, 4Mb/s mode, last channel = ch 63, 8Mb/s mode, last channel = ch 127 Figure 12 - ...

Page 28

MT90823 CMOS CLK (ST-BUS or) (WFPS mode) CLK (GCI mode Valid Data STo t ZD HiZ STo t XCD CSTo Figure 14 - Serial Output and External Control HiZ V CT Figure 15 ...

Page 29

AC Electrical Characteristics - Multiplexed Bus Timing (Mode 1) Characteristics 1 ALE pulse width 2 Address setup from ALE falling 3 Address hold from ALE falling 4 RD active after ALE falling 5 Data setup from DTA Low on Read ...

Page 30

MT90823 CMOS AC Electrical Characteristics - Multiplexed Bus Timing (Mode 2) Characteristics 1 AS pulse width 2 Address setup from AS falling 3 Address hold from AS falling 4 Data setup from DTA Low on Read 5 CS hold after ...

Page 31

AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising 6 ...

Page 32

Pin #1 Corner 3.00*45 (4x) 20.00 REF 30 Typ. C Seating Plane Package Outlines ...

Page 33

Package Outlines Dim D General- (lead coplanarity) A Notes Not ...

Page 34

... Mitel. This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specifi ...

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