TRCV012G7 Agere Systems, TRCV012G7 Datasheet

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TRCV012G7

Manufacturer Part Number
TRCV012G7
Description
Limiting amplitier, clock recovery, 1:16 data demultiplexer. BiCMOS. 2.5 Gbits/s and 2.7 Gbits/s
Manufacturer
Agere Systems
Datasheet

Specifications of TRCV012G7

Case
??QFP
Dc
01+
August 2000
Features
* Telcordia Technologies is a registered trademark of Bell Com-
TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s)
munications Research, Inc.
TRCV012G5 supports OC-48/STM-16 data rate
TRCV012G7 supports:
Fully-integrated limiting amplifier, clock recovery,
1:16 data demultiplexer
No reference clock required for CDR
2.5 Gbits/s data output and 2.5 GHz recovered
clock output available for wavelength division
multiplex (WDM) or regenerator applications
Programmable limiting amplifier offset
Programmable data sampling phase
Additional CML serial data input for system
loopback
Parity bit generation
Analog and digital loss of signal (LOS) indicators
Optional demultiplexer powerdown mode
conserves power
Single 3.3 V supply
Available in either MBIC 025 BiCMOS technology
or lower-power MBIC 025 silicon germanium
BiCMOS technology
High-speed LVPECL digital I/O
Jitter tolerance, transfer, and generation compliant
with the following:
— Telcordia Technologies * GR-253
— ITU-T G.825
— ITU-T G.958
Loss of signal compliant with the following:
— Telcordia Technologies GR-253
— OC-48/STM-16 data rate
— RS (255, 239) forward error correction (FEC)
OC-48/STM-16 data rate
Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer
Applications
Description
The Lucent Technologies Microelectronics Group
TRCV012G5 operates at the OC-48/STM-16 data
rate of 2.5 Gbits/s. The TRCV012G7 device operates
at either 2.5 Gbits/s or the RS FEC OC-48/STM-16
data rate of 2.7 Gbits/s. For clarity, this data sheet
refers to the TRCV012G5 serial data rate as
2.5 Gbits/s and the parallel data and reference clock
frequency as 155 MHz. (The precise rates are
2.48832 Gbits/s and 155.52 MHz.) When using the
TRCV012G7 at the FEC rate, the 2.5 Gbits/s data
rate should be interpreted as 2.7 Gbits/s and the par-
allel and clock frequency should be interpreted as
166 MHz. (The precise rates are 2.66606 Gbits/s and
166.62 MHz.)
The devices contain a limiting amplifier with 30 dB
gain, a clock and data recovery PLL with high-speed
serial clock and data outputs, and a 1:16 demulti-
plexer with differential PECL data and clock outputs.
The device provides improved optical receiver perfor-
mance when used in optically amplified systems due
to a direct slice adjust input pin and a 6 ps adjust-
ment capability in the slicing decision time. Both
devices are available in either BiCMOS or in SiGe
BiCMOS technology for lower power operation.
SONET/SDH line termination equipment
SONET/SDH add/drop multiplexers
SONET/SDH cross connects
SONET/SDH test equipment

Related parts for TRCV012G7

TRCV012G7 Summary of contents

Page 1

... August 2000 TRCV012G5 (2.5 Gbits/s) and TRCV012G7 (2.5 Gbits/s and 2.7 Gbits/s) Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Features TRCV012G5 supports OC-48/STM-16 data rate TRCV012G7 supports: — OC-48/STM-16 data rate — RS (255, 239) forward error correction (FEC) OC-48/STM-16 data rate Fully-integrated limiting amplifier, clock recovery, ...

Page 2

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Contents Features .................................................................................................................................................................... 1 Applications ............................................................................................................................................................... 1 Description.................................................................................................................................................................1 Pin Information ..........................................................................................................................................................4 Functional Overview ................................................................................................................................................10 Limiting Amplifier .....................................................................................................................................................10 Limiting Amplifier Operation..................................................................................................................................10 Clock and Data Recovery (CDR).............................................................................................................................11 Clock Recovery Operation ....................................................................................................................................11 Clock Recovery PLL Loop Filter ...........................................................................................................................11 CDR Acquisition Time...........................................................................................................................................11 CDR Generated Jitter ...........................................................................................................................................11 CDR Input Jitter Tolerance ...

Page 3

... Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer MUTEDMX SAMPLER CIRCUIT ENDATCK 1 CHARGE 0 VCO PUMP DIVIDE BY 16 LFP LFN VCP VCN Figure 1. Functional Block Diagram TRCV012G5 and TRCV012G7 ENCK2G5N CK2G5P CK2G5N 0 END2G5N D2G5P 1 D2G5N MUTE2G5N MUTE2G5 MUTEDMXN D0P D0N D1P D1N D15P D15N PARITYP ...

Page 4

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Pin Information GND 1 AST4 2 AST3 3 AST2 4 AST1 5 AST0 6 GND CCD V 9 CCA V 10 CCA GND GND 15 VCN 16 LFN 17 LFP 18 VCP 19 GND 20 GND CCA V 23 CCA V 24 CCLA ...

Page 5

... August 2000 Pin Information (continued) Note: In Table 1, when operating the TRCV012G7 device at the OC-48/STM-16 rate, 2.5 Gbits/s should be inter- preted as 2.48832 Gbits/s. When operating the TRCV012G7 device at the RS FEC OC-48/STM-16 rate, 2.5 Gbits/s should be interpreted as 2.66606 Gbits/s. (A similar interpretation should be made for 2.5 GHz.) Table 1. Pin Descriptions— ...

Page 6

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Pin Information (continued) Table 1. Pin Descriptions—2.5 Gbits/s and Related Signals (continued) Pin Symbol* 43 DATCKP 44 DATCKN 124 ENDATCKN 46 DATAP 47 DATAN 125 ENDATAN 37 ASTREF 2 AST4 3 AST3 4 AST2 5 AST1 6 AST0 * Differential pins are indicated by the P and N suffixes. For nondifferential pins the end of the symbol name designates active-low. ...

Page 7

... Pin Information (continued) Note: In Table 2, when operating the TRCV012G7 device at the OC-48/STM-16 rate, 155 Mbits/s should be inter- preted as 155.52 Mbits/s. When operating the TRCV012G7 device at the RS FEC OC-48/STM-16 rate, 155 Mbits/s should be interpreted as 166.62 Mbits/s. (A similar interpretation should be made for 155 MHz.) Table 2. Pin Descriptions— ...

Page 8

... Reference Clock Input (155 MHz). This clock is optional. If applying the REFCLKP/N, set the REFCLKP/N to one of the following frequencies: 155.52 MHz if using the TRCV012G5, or the TRCV012G7 at the 0C-48/STM-16 rate of 2.48832 GHz. 166.62 MHz if using the TRCV012G7 at the RS FEC 0C-48/STM-16 rate of 2.66606 GHz CMOS Reference Select to PLL ...

Page 9

... Power Limiting Amplifier Power Supply (3.3 V). I Power Digital Power Supply (3.3 V). I Ground Ground. No Connection. These pins must be left open internal pull-down resistor on this pin, I TRCV012G5 and TRCV012G7 Name/Description internal termination resis- unless otherwise specified. CC Name/Description internal termination resis- 9 ...

Page 10

... Functional Overview The Lucent Technologies Microelectronics Group TRCV012G5 operates at the OC-48/STM-16 data rate of 2.5 Gbits/s.* The TRCV012G7 device operates at either 2.5 Gbits/s or the RS FEC OC-48/STM-16 data rate of 2.7 Gbits/s. The device performs the data detection, clock recovery, and 1:16 demultiplexing operations required to support 2.5 Gbits/s applications compliant with Telcordia Technologies and ITU standards. A differential limiting amplifier with an adjustable threshold amplifies the 2 ...

Page 11

... This denotes the device specification for system SONET/SDH compliance when the loop filter in Table 5 and Figure 4 is used. Lucent Technologies Inc. Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer 0.47 F ± 10 ± 20% 82.5 ± 5% 100 k ± 5% LFP/VCP LFN/VCN Typical (Device)* 0.06 0.008 TRCV012G5 and TRCV012G7 C 3 Max Unit 0.10 UIp-p 0.01 UIrms 5-8061(F).a 11 ...

Page 12

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Clock and Data Recovery (CDR) CDR Input Jitter Tolerance The limiting amplifier plus CDR’s jitter tolerance performance meets the requirement shown in Figure 5 on page 13 when the limiting amplifier’s input signal is within the valid level range given in Table 9 on page 20, the loop filter in Figure 4 is used, and the data sequence is a valid OC-48 SONET/SDH signal ...

Page 13

... Lucent Technologies Inc. Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer (continued) (600 Hz, 15 UIp-p) (6 kHz, 1.5 UIp-p) 1k 10k FREQUENCY (Hz) Figure 5. Receiver Jitter Tolerance (2 MHz, 0.1 dB) 100k 1M FREQUENCY (Hz) Figure 6. Receiver Jitter Transfer TRCV012G5 and TRCV012G7 (100 kHz, 1.5 UIp-p) (1 MHz, 0.15 UIp-p) 100k 1M 10M 5-8069(F)r.1 10M 100M 5-8062(F)r.2 13 ...

Page 14

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Clock and Data Recovery (CDR) Data Path Configuration Option (ENDATAN) Either the limiting amplifier (LAINP/ CML logic level input (DATAP/N) can be selected as the source of the 2.5 Gbits/s data signal. The DATAP/N input can be used if the limiting amplifier is not needed can be used as a system loopback path when the limiting amplifier is the normal data path ...

Page 15

... AST circuitry The AST control bit configurations and corresponding offset times are shown in Table 7 Table 7. Adjustable Sampling Time (AST) Control Code Note: When operating the TRCV012G7 at the FEC rate, the 6.25 ps step should be scaled down by 7%. AST[4:0] Time Offset (ps) 01111 – ...

Page 16

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Loss of Signal Detection The loss of signal circuits are used to detect the conditions of low input signal level or no data transitions at the input. The LOSDN and LOSAN signals can be processed and/or filtered to meet various system-dependent requirements on declaring loss of signal ...

Page 17

... The 155 MHz low-speed clock output (CK155P, CK155N) can be forced to logic low by setting MUTE155N, which is an active-low CMOS input with an internal pull-up resistor. A ground or logic low applied to MUTE155N mutes the CK155P/N output. Lucent Technologies Inc. Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer D14 D1 TIME TRCV012G5 and TRCV012G7 D0 D15 (LSB) (D0 RECEIVED LAST) 5-8063(F).a 17 ...

Page 18

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer CML Output Structure (Used on Pins D2G5P/N, CK2G5P/N) The CML architecture is essentially a current-steering mechanism combined with an amplifier. This makes the out- put swing of the signal a function of the termination resistor and the programmable output current. The user should connect external termination resistors from the CML output pins to V vide a dc path when using an ac-coupled load ...

Page 19

... Symbol Min — 3.135 — — (See Table 11, (See Table 11, V Table 13 Table 15.) Table 15 –40 A — — — D TRCV012G5 and TRCV012G7 Unit V °C V Typ Max Unit 3.3 3.465 — — (See Table 11, Table 13, Table 13, Table 15.) — 85 — 125 2.5 3.43 1.45 1. ...

Page 20

... When using the TRCV012G5 device, a 155.52 MHz differential LVPECL clock can be applied to the REFCLKP/N input. When using the TRCV012G7 device at the OC-48/STM-16 rate, a 155.52 MHz differential LVPECL clock can be applied to the REFCLKP/N input. When using the TRCV012G7 device at the RS FEC OC-48/STM-16 rate, a 166.62 MHz differential LVPECL clock can be applied to the REFCLKP/N input ...

Page 21

... Conditions — — GND GND IN Parameter Conditions — TRCV012G5 and TRCV012G7 Min Typ Max –1165 — –880 CC –1810 — –1475 CC — — — — Min Typ Max – 1.31 V – 1.20 V – 0. – ...

Page 22

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Electrical Characteristics LVPECL, CMOS, CML Input and Output Pins Table 15. CML Input Pin dc Characteristics Applicable Symbol Parameter Pins DATAP/N, V Input Voltage Low IL DATCKP/N V Input Voltage High IH Table 16. CML Output Pin dc Characteristics Applicable ...

Page 23

... Transition Skew Rise to Fall SKEW Lucent Technologies Inc. Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer t PERIOD t DD1 DATA 1 DATA 2 t DD2 PARITY 1 PARITY 2 Parameter Conditions All signals differential TRCV012G5 and TRCV012G7 DATA 3 PARITY 3 5-7726(F).fr.4 Min Typ Max Unit — 6.43 — ns — 6.00 — ...

Page 24

... TRCV012G5 and TRCV012G7 Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Timing Characteristics (continued) Output Timing (continued) The timing relationship between the 2.5 GHz or 2.7 GHz output clock (CK2G5P/N) and the 2.5 Gbits/s or 2.7 Gbits/s output data (D2G5P/N) is shown in Figure 11. CK2G5P OUTPUT CK2G5N OUTPUT D2G5P/N Figure 11. Transmit Timing Waveform with 2.5 GHz or 2.7 GHz Clock The 2 ...

Page 25

... Dimensions are in millimeters. 17.20 0.20 13.89 0.10 8.13 (REF) 128 DETAIL A 11.43 0.18 0.20 0.06 0.50 (TYP) 2.89 8.13 (REF) (REF) 2 (8.13) x 0.305 HEAT SINK Lucent Technologies Inc. Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer 2.89 (REF) 103 102 5.87 (REF) 17.52 0.18 19.86 0.10 8.13 (REF 2.80 (REF) 3.30 (REF) 0.38 (REF) 0.000 TO 0.100 TRCV012G5 and TRCV012G7 1.600 0.150 23.20 0.20 0.800 0.150 DETAIL A 5-8416(F)r.2 25 ...

Page 26

... Thermal Considerations (MBIC 025 BiCMOS and MBIC 025 SiGe BiCMOS) The TRCV012G5 and TRCV012G7 devices use a square heat sink on the bottom of the package for heat dissipa- tion. This heat sink is planar with the lead surface which contacts the board. For optimum heat transfer, the heat sink should be soldered to the application board using the suggested footprint shown above ...

Page 27

... Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer Package Temperature 128-pin QFP –40 °C to +85 °C 128-pin QFP –40 °C to +85 °C 128-pin QFP –40 °C to +85 °C 128-pin QFP –40 °C to +85 °C — TRCV012G5 and TRCV012G7 Comcode (Ordering Number) 108419953 108700675 108560343 108700683 — — 27 ...

Page 28

Limiting Amplifier, Clock Recovery, 1:16 Data Demultiplexer For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447 , ...

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