AM79C983AKC Advanced Micro Devices, AM79C983AKC Datasheet
AM79C983AKC
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AM79C983AKC Summary of contents
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... AUI ports can be turned off individually (without ex- ternal circuitry) to allow the switching of transceiver This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice ...
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IMR2 device that transfers the information to a MAC For application examples on building fully-managed repeaters using the IMR2 and ...
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BLOCK DIAGRAM DO AUI DI Port CI RDO RAUI RDI Port RCI PDO PAUI PDI Port 0 PCI PDO PAUI PDI Port 11 PCI PDAT PCLK PENAI PENAO PTAG PDRV MCLK RST XENA ...
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RELATED AMD PRODUCTS Part No. Description Am79C981 Integrated Multiport Repeater+ (IMR+™) Am79C982 b asic Integrated Multiport Repeater ( b IMR™) Am79C987 Hardware Implemented Management Information Base (HIMIB™) Am79C988A Quad Integrated Ethernet Transceiver (QuIET™) Am7990 Local Area Network Controller for Ethernet ...
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CONNECTION DIAGRAM 1 DO– 2 DO+ 3 DI– 4 DI+ 5 CI– 6 CI+ 7 DVSS MACEN 8 COL 9 ACK 10 11 XMODE REQ 12 DAT 13 14 JAM 15 VDD 16 ECLK FRAME 17 18 DVSS PDRV 19 ...
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LOGIC SYMBOL AUI RAUI PAUI (12) Packet Report Port LOGIC DIAGRAM RAUI Port AUI Port PAUI Port DAT REQ DI ACK CI COL JAM ...
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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combi- nation) is formed by a combination of the elements below. K Am79C983A Valid Combinations Am79C983A KC, KC ...
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TABLE OF CONTENTS DISTINCTIVE CHARACTERISTICS .................................................................................................... 1 GENERAL DESCRIPTION................................................................................................................... 1 BLOCK DIAGRAM ............................................................................................................................... 3 RELATED AMD PRODUCTS............................................................................................................... 4 CONNECTION DIAGRAM .................................................................................................................... 5 LOGIC SYMBOL ................................................................................................................................... 6 LOGIC DIAGRAM ................................................................................................................................ 6 ORDERING INFORMATION................................................................................................................. 7 Standard Products .......................................................................................................................... 7 PIN DESIGNATIONS .......................................................................................................................... ...
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Microprocessor Interface .............................................................................................................. 29 Management Functions .......................................................................................................... 29 Status Register ................................................................................................................ 30 Register Bank 0: Repeater Registers .............................................................................. 30 Source Address Match Register .............................................................................. 30 Total Octets.............................................................................................................. 31 Transmit ...
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SQE Test Status ...................................................................................................... 39 Register Bank 5: RMON Registers .................................................................................. 39 etherStatsOctets ...................................................................................................... 39 etherStatsPkts.......................................................................................................... 39 etherStatsBroadcastPkts.......................................................................................... 40 etherStatsMulticastPkts............................................................................................. 40 etherStatsCRCAlignErrors ........................................................................................ 40 etherStatsUndersizePkts.......................................................................................... 40 etherStatsOversizePkts............................................................................................ 40 etherStatsFragments................................................................................................ 40 etherStatsJabbers .................................................................................................... 40 etherStatsCollisions ................................................................................................. 40 etherStats64Octets .................................................................................................. 40 etherStats65to127Octets ...
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Expansion Bus Asynchronous Clock (ECLK) Timing ................................................................... 54 Expansion Bus Input Timing - Synchronous Mode ....................................................................... 55 Expansion Bus Output Timing - Synchronous Mode .................................................................... 55 Expansion Port Collision Timing - Synchronous Mode ................................................................. 56 Packet Report Port Timing............................................................................................................ 56 ...
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PIN DESIGNATIONS Listed by Pin Number Pin No. Pin Name Pin No MACEN 41 9 COL 42 ...
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PIN DESCRIPTION Pseudo AUI Pins PDO 0-11 Pseudo AUI Data Output Output/High Impedance PDO is a single-ended output driver. PDO can be placed into a high impedance state, allowing multiple IMR2 devices to connect to a single QuIET device (port ...
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COL Collision Input, Active LOW When this pin is asserted by an external arbiter, it sig- nifies that more than one IMR2 device is active and that each IMR2 device should generate the Collision Jam Sequence independently. ECLK Bus Clock ...
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PTAG Packet Tag Output, HIGH Impedance, Active LOW PTAG indicates when the status frame is being trans- mitted over PDAT asserted when the status frame is transmitted. Microprocessor Interface D[7:0] Microprocessor Data Input/Output These pins are inputs when ...
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DIR Direction Output DIR sets the direction of data on SDATA[3:0] The set- tings are as follows: DIR[1:0] Function Transceiver (QuIET device) drives SDATA with 00 status and device ID. 01 SDATA is a high impedance output. 10 SDATA is ...
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FUNCTIONAL DESCRIPTION Overview The Am79C983A Integrated Multiport Repeater 2 de- vice provides a system-level solution to designing IEEE 802.3 managed repeaters. It includes 12 pseudo AUI (PAUI) ports for single-ended connections to external transceivers. The IMR2 device interfaces directly with ...
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Standard reconnection algorithm—A data packet longer than 512-bit times (nominal) is transmitted or re- ceived by the partitioned port without a collision. b. Alternate reconnection algorithm—A data packet longer than 512-bit times (nominal) is transmitted by the partitioned port ...
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C Command (C) Port 8 Status 8 Register Register Select Node 5 Processor Port A - AUI Port AR - RAUI Port EP - Expansion Port ICR - ...
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Reg. Register Bank 0 No. Repeater Registers Port Partition Status 0 Change Interrupt Runts with Good FCS 1 Interrupt Link Status Change 2 Interrupt Loopback Error Change 3 Interrupt 4 Polarity Change Interrupt SQE Test Error Change 5 Interrupt Source ...
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Register Bank 4 Reg. No. Port Status Registers 0 Partitioning Status of Ports 1 2 Link Test Status of Ports 3 Loopback Error Status 4 Receive Polarity Status 5 SQE Test Status ...
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Detailed Functions This section describes the detailed functional behavior of the IMR2 device. Where necessary, the behavior is defined in terms of state machines. Note that this is a conceptual definition and the actual implementation may be different. Reset Hardware ...
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Synchronous Mode Operation While operating in the synchronous mode, the expan- sion bus pins are Data (DAT), JAM, Request (REQ), Acknowledge (ACK), and Collision (COL). DAT and JAM are bidirectional signals. REQ is an output. ACK and COL are inputs. ...
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DAT and JAM signals. The external arbiter asserts ACK if one and only one IMR2 device has REQ asserted. This allows the corresponding IMR2 device to drive the DAT ...
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Preamble and SFD Front of Original Packet (min 14 Octets long) Stat 1 Field Device ID Port Number (4 Bits) Stat 2 Field LSB Frame Size (in Octets) MSB Frame Size (in Octets) New FCS (4 Octets) BROAD - Broadcast ...
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PDAT Pre SFD DA SA PCLK PENAO PDRV PTAG Error Packet Statistics Sample Error Status is an 8-byte 4-deep FIFO that con- tains statistical data on each packet having errors. The data is read in the following order: Port Number ...
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In the QuIET device mode, DIR[1] has the following values: DIR[1] 0 QuIET device drives SDATA with sta- tus and device ID. 1 IMR2 device drives QuIET device with commands. DIR[1] continually cycles. The state of DIR changes once every ...
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LD[7:0] BSEL CRS COLX PART LINK POL Figure 5. Visual Monitor Signals CRS and COLX are the only valid attributes for the Ex- pansion Bus. Therefore, when BSEL is HIGH, LD[6] has the Expansion Bus attribute for CRS and COLX. ...
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Pre- ferred Source Address Register. The interrupt is set when there is a mismatch. If the Automatic Intrusion Control register bit is set, the port is disabled if there is no match between ...
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Unless otherwise indicated, the discussion of registers that are concerned with status or control on the IMR2 device will have the following format. IMR2 Device Registers D Port Read/Write Byte 0 Byte 1 0 EP/0 ...
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Total Octets Address: 1110 1100 D Port Read/Write bit 7 Byte 0 Byte 1 Byte 2 bit 31 Byte This is a 4-byte attribute register whose contents are in- cremented while the repeater is repeating packet data. ...
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M Transceiver X3-X0 0 QuIET Device Reserved Repeater Device and Revision Register Address: 1111 1100 This is a read only register. The 8-bit quantity read has the following format: D Port Read ...
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TPn/SPn 0 Link Test state unchanged 1 Link Test state changed Loopback Error Change Interrupt Address: 1110 0011 If a port is connected to a MAU which does not loop- back data from during transmission that port ...
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Pn/AUI/RAUI/ match 1 Source address matches the Source Address Match Register Note: This function is useful for mapping stations to ports in a network. Data Rate Mismatch Interrupt Address: 1110 1010 A bit is set when the data ...
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Pn/AUI/RAUI/EP 0 Runts with Valid FCS Interrupt masked (disabled) 1 Runts with Interrupt enabled Link Status Change Interrupt Enable Address: 1110 0010 Setting any of the bits in this register causes the INT pin to be driven when there is ...
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Multicast Address Pass Enable Address: 1110 1001 Setting EP disables packet compression on packets with multicast addresses. D Port Read/Write Byte 0 Byte MSB EP 0 Packet compression on ...
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Register Bank 3: Port Control Registers These registers are accessed by writing the bit pattern 0000 0011 into the C register. All registers can be read from as well as written to. Alternative Reconnection Algorithm Enable Address: 1110 0000 The ...
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This feature is useful when implementing port switching. The IMR2 device connected to the QuIET device serial interface will still report correct status on the Link and Polarity LEDs. The ports default to the XENA value on reset. ...
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Pn/AUI/RAUI/EP 0 Last Source Address Lock disabled 1 Last Source Address Lock enabled Note: Setting a bit on this register invalidates the cor- responding Source Address Changes Register. Register Bank 4: Port Status Registers These registers are accessed by writing ...
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Address: 1110 0010 The value in this register represents the total number of valid packets received that were addressed to a broadcast address. etherStatsMulticastPkts Address: 1110 0011 The value in this register represents the total number of valid packets ...
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The data format is as follows: D Port Read/Write Byte DRE RNT S Byte 1 bit 23 Byte 2 Byte 3 Byte 4 Byte ...
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The contents of all attribute registers are maintained during hardware or software reset. These attributes and their definitions comply with the IEEE 802.3 Repeater Management standard, Section19 ( Layer Management for 10 Mb/s Baseband Repeaters brief description of ...
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Short Events Address: 1110 0101 D Port Read bit 7 Byte 0 Byte 1 Byte 2 bit 31 Byte 3 MSB Short Events is a read-only attribute that counts the number of instances where activity is detected with a duration ...
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Auto Partitions Address: 1110 1011 D Port Read Byte 0 bit 7 Byte 1 Byte 2 bit 31 Byte 3 MSB Auto Partitions is a read-only attribute that counts the number of instances where the repeater has partitioned this port ...
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SYSTEM APPLICATIONS IMR2 to QuIET Connection The IMR2 device provides a system solution to design- ing repeaters. It can be used with the QuIET transceivers to design 10BASE-T hubs or with other types of MAUs for 10BASE2 or 10BASE-FL hubs. ...
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IMR2 PDO0 PDI0 PCI0 PDO1 PDI1 PCI1 PDO2 PDI2 PCI2 PDO3 PDI3 PCI3 MCLK RST Note: Common mode chokes may be required. Figure 7. Simplified 10BASE-T Connection QuIET ...
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Am79C983 0.1 F PDO 16 K 10K 0.1 F PDI 10K 10K 0.1 F PCI 10K Figure 8. PAUI Interface to non-QuIET Device Transceiver Am79C940 DO+ DO– ...
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Am79C90 (C-LANCE) CLSN RCLK RX RENA TENA TX TCL Generator Figure 10. PR Port Connection to an Am79C90 C-Lance Port Switching Port switching allows the movement of individual ports between multiple Ethernet collision domains via soft- ware. This capability enables ...
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Backplane 0 PDO PDI PCI PDO PDI PCI Am79C983 PDO PDI PCI IMR2 0 PDO PDI PCI SDATA[0] DIR[1] Backplane 1 PDO PDI PCI PDO PDI Am79C983 PCI PDO ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . .. – +150 C Ambient Temperature Under Bias Supply Voltage ...
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SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified Parameter Symbol Parameter Description Clock and Reset Timing t MCLK Clock Period MCLK t MCLK Clock HIGH MCLKH t MCLK Clock LOW MCLKL t MCLK Rise Time MCLKR t MCLK Fall Time ...
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Parameter Symbol Parameter Description t MCLK HIGH to DAT/JAM Driven MHDR t MCLK HIGH TO DAT/JAM Not Driven MHDZ t DAT/JAM Setup Time to MCLK MDSET t DAT/JAM Hold Time from MCLK MDHOLD t COL/ACK Setup Time to MCLK MASET ...
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PDI pulses narrower than tPWKPDI (min) will maintain internal PDI carrier sense on; PDI pulses wider than tPWKPDI (max) will turn internal PDI carrier sense off. 9. PCI pulses narrower than tPWOPCI (min) will be rejected; PCI pulses wider ...
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KEY TO SWITCHING WAVEFORMS WAVEFORM SWITCHING WAVEFORMS Figure 13. Expansion Bus Asynchronous Clock (ECLK) Timing INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing ...
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SWITCHING WAVEFORMS MCLK TCLK* REQ ACK COL DAT/JAM *TCLK illustrates internal IMR2 chip clock phase relationships Figure 14. Expansion Bus Input Timing - Synchronous Mode MCLK TCLK* REQ REQ ACK ACK COL COL DAT/JAM *TCLK illustrates internal IMR2 chip clock ...
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SWITCHING WAVEFORMS MCLK TCLK* REQ ACK COL DAT/JAM *TCLK illustrates internal IMR2 chip clock phrase relationships Figure 16. Expansion Port Collision Timing - Synchronous Mode PCLK PDAT PENAO ECLK REQ ACK COL DAT Figure 18. Expansion Port Input Timing - ...
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SWITCHING WAVEFORMS ECLK REQ ACK COL DAT Figure 19. Expansion Port Output Timing - Asynchronous Mode MCLK PDO tPDOTD PCI VASQ tPWKPCI tPWOPCI tELDR Figure 20. PAUI PDO Transmit ...
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SWITCHING WAVEFORMS PDI VASQ tPWKPDI tPWOPDI MCLK tDOTD DO+ DO– RDI VASQ tPWKDI tPWODI tPWKPDI Figure 22. PAUI Receive tDOETD tDOTR tDOTF Figure 23. (R)AUI Timing ...
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SWITCHING WAVEFORMS C/D CS RD, WR RDY D7–0 D7–0 Figure 25. Microprocessor Bus Interface Timing tCDS tCSS tCSH tRDYD tRDYH tDOUT Read Data tDIS Write Data Am79C983A tCDH tREST ...
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... Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof, and IMR2, QuIET, HIMIB, PAUI, and RAUI are trademarks of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. ...