M5M4V64S40ATP-10L MITSUBISHI, M5M4V64S40ATP-10L Datasheet
M5M4V64S40ATP-10L
Related parts for M5M4V64S40ATP-10L
M5M4V64S40ATP-10L Summary of contents
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... Synchronous DRAM Some of contents are subject to change without notice. DESCRIPTION The M5M4V64S40ATP is a 4-bank x 1048576-word x 16-bit Synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M5M4V64S40ATP achieves very high speed data rate up to 125MHz, and is suitable for main memory or graphic memory in computer systems ...
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... Synchronous DRAM BLOCK DIAGRAM Memory Array Bank #0 Mode Register Address Buffer A0-11 BA0,1 Type Designation Code M5M4V64S40ATP-8A,-8L,-8, -10L, -10 DQ0-15 I/O Buffer Memory Array Memory Array Bank #1 Bank #2 Control Circuitry Control Signal Buffer Clock Buffer ...
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... Power Supply VddQ, VssQ Power Supply M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Master Clock: All other inputs are referenced to the rising edge of CLK. Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh ...
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... Mar'98 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM BASIC FUNCTIONS The M5M4V64S40ATP provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. ...
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... READA Precharge Auto-Refresh REFA Self-Refresh Entry REFS Self-Refresh Exit REFSX Burst Terminate TBST Mode Register Set MRS H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address M5M4V64S40ATP-8A,-8L,-8, -10L, -10 CKE CKE /CS /RAS /CAS n ...
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... READ M5M4V64S40ATP-8A,-8L,-8, -10L, -10 /CAS /WE Address BA, CA, A10 BA, A10 Op-Code Mode-Add ...
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... WRITE with AUTO L H PRECHARGE M5M4V64S40ATP-8A,-8L,-8, -10L, -10 /CAS /WE Address BA, CA, A10 L L BA, CA, A10 BA, A10 Op-Code Mode-Add X ...
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... X ROW ACTIVATING WRITE RE- COVERING M5M4V64S40ATP-8A,-8L,-8, -10L, -10 /CAS /WE Address BA, CA, A10 BA, A10 Op-Code Mode-Add ...
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... ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. M5M4V64S40ATP-8A,-8L,-8, -10L, -10 /CAS /WE Address X X ...
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... CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. M5M4V64S40ATP-8A,-8L,-8, -10L, -10 /CS /RAS /CAS /WE ...
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... Synchronous DRAM SIMPLIFIED STATE DIAGRAM MODE REGISTER TBST (for Full Page) CKEL WRITE SUSPEND CKEH CKEL WRITEA SUSPEND CKEH POWER APPLIED POWER M5M4V64S40ATP-8A,-8L,-8, -10L, -10 REFS MRS IDLE SET CKEH CLK SUSPEND ACT CKEL CKEH ROW ACTIVE WRITE WRITEA READA ...
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... CL /CAS LATENCY LATENCY MODE BURST WRITE MODE SINGLE BIT 1 M5M4V64S40ATP-8A,-8L,-8, -10L, - LTMODE MITSUBISHI ELECTRIC MITSUBISHI LSIs CLK /CS /RAS /CAS ...
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... M5M4V64S40ATP-8A,-8L,-8, -10L, - Burst Length Column Addressing Sequential ...
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... For BL=FP (Full Page), the TBST (Burst Terminate) command must be used to stop the output of data. Burst Length Timing( CL=2 ) tRCD CLK ACT Command READ X Y Address M5M4V64S40ATP-8A,-8L,-8, -10L, -10 READ ...
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... Any command (READ, WRITE, PRE, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. M5M4V64S40ATP-8A,-8L,-8, -10L, -10 tRCmin ACT ...
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... A11 Xa BA0 READ with Auto-Precharge (BL=4, CL=3) CLK ACT Command A0-9 Xa A10 Xa Xa A11 00 BA0,1 DQ CLK ACT Command CL=3 DQ CL=2 DQ M5M4V64S40ATP-8A,-8L,-8, -10L, -10 READ ACT tRCD Qa0 /CAS latency BL + tRP READ tRCD Qa0 Internal precharge start READ Auto-Precharge Timing (BL=4) READ BL ...
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... ACT Command A0-9 Xa A10 A11 BA0 CLK Command ACT A0-9 Xa A10 Xa A11 Xa BA0 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Multi Bank Interleaving WRITE (BL=4) Write ACT tRCD tRCD Da0 Da1 Da2 Da3 WRITE with Auto-Precharge (BL=4) Write tRCD tWR Da0 Da1 ...
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... A single write operation is enabled by setting A9= single write operation, data is only written to the column address specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0.) CLK Command ACT X Address DQ M5M4V64S40ATP-8A,-8L,-8, -10L, - ...
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... DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. CLK READ Command Yi A0-9 A10 0 A11 00 BA0,1 DQM Q D M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Read Interrupted by Read (BL=4, CL=3) READ READ Qai0 Qaj0 Qaj1 Qbk0 Qbk1 Read Interrupted by Write (BL=4, CL=3) Write ...
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... CLK. A PRE command to output disable latency is equivalent to the /CAS Latency result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4. CLK Command DQ Command CL=3 DQ Command DQ Command DQ Command CL=2 DQ Command DQ M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Read Interrupted by Precharge (BL=4) READ PRE Q0 READ PRE Q0 READ PRE Q0 READ PRE Q0 Q1 READ PRE Q0 Q1 ...
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... The READ to TBST interval is a minimum of one CLK. TBST is mainly used to interrupt FP bursts. The figures below show examples, of how the output data is terminated with TBST. Read Interrupted by Burst Terminate(BL=4) CLK Command DQ Command CL=3 DQ Command DQ Command DQ CL=2 Command DQ Command DQ M5M4V64S40ATP-8A,-8L,-8, -10L, -10 READ TBST READ TBST READ TBST Q0 READ TBST ...
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... WRITE to READ interval is minimum 1 CLK. The input data the interrupting READ cycle is "don't care". CLK Command Write READ A0 A10 A11 BA0,1 00 DQM Dai0 DQ M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Write Interrupted by Write (BL=4) Write Daj0 Daj1 Dbk0 Dbk1 Dbk2 Write Interrupted by Read (BL=4, CL= ...
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... The WRITE to TBST minimum interval is one CLK. Write Interrupted by Burst Terminate(BL=4) CLK WRITE Command Yi A0-9 0 A10 0 BA DQMU/DQML (DQM) DQ Dai0 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Write Interrupted by Precharge (BL=4) PRE tWR tRP 0 00 Dai1 Dai2 TBST Dai1 Dai2 MITSUBISHI ELECTRIC MITSUBISHI LSIs ACT Xb ...
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... Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command. CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1 Auto Refresh on All Banks M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Auto-Refresh NOP or DESELECT minimum tRC MITSUBISHI ELECTRIC MITSUBISHI LSIs Auto Refresh on All Banks 24 ...
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... After tRC from REFSX all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1 Self Refresh Entry M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Self-Refresh Stable CLK Self Refresh Exit MITSUBISHI ELECTRIC MITSUBISHI LSIs NOP tSRX new command X 00 ...
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... CKE int.CLK CLK CKE Command PRE CKE Command ACT CLK CKE Command Write DQ D0 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Power Down by CKE Standby Power Down NOP NOP Active Power Down NOP NOP DQ Suspend by CKE READ MITSUBISHI ELECTRIC MITSUBISHI LSIs NOP NOP NOP ...
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... During writes, DQMU/L masks input data word by word. DQMU/L to write mask latency is 0. During reads, DQMU/L forces output to Hi-Z word by word. DQMU/L to output Hi-Z latency is 2. CLK Command Write DQMU masked by DQMU/L=H M5M4V64S40ATP-8A,-8L,-8, -10L, -10 DQM Function READ D2 D3 MITSUBISHI ELECTRIC MITSUBISHI LSIs Q0 Q1 ...
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... Vdd = VddQ = 3.3 ± 0.3v, Vss = VssQ = 0v, unless otherwise noted) Symbol CI(A) Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Conditions with respect to Vss with respect to VssQ with respect to Vss with respect to VssQ °C Parameter Supply Voltage Supply Voltage ...
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... Parameter VOH (DC) High-Level Output Voltage (DC) VOL (DC) Low-Level Output Voltage (DC) IOZ Off-state Output Current Input Current I I M5M4V64S40ATP-8A,-8L,-8, -10L, -10 Test Conditions tRC=min, tCLK=min, BL=1, CL=3 tRC=90ns, tCLK=min, BL=1, CL=3 all banks idle, tCLK=min all banks idle, tCLK=min all banks active, tCLK=min all banks active, tCLK=min all banks active, tCLK=min, BL=4, ...
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... Self Refresh Exit time tREF Refresh Interval time Note:1 The timing requirements are assumed tT=1ns longer than 1ns, (tT-1)ns should be added to the parameter ACT commands are allowed within tRC. CLK Signal M5M4V64S40ATP-8A,-8L,-8, -10L, -10 0.8V to 2.0V 1.4V Limits -8A Min. Max. Min. CL ...
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... Delay time, output low tOLZ impedance from CLK Delay time, output high tOHZ impedance from CLK Note:3 If tr(clock rising time) is longer than 1ns, (tT/2-0.5)ns should be added to the parameter. Output Load Condition 50 V OUT 50pF CLK DQ M5M4V64S40ATP-8A,-8L,-8, -10L, -10 -8A Min. Max. CL=2 8 CL=3 6 2 =1.4V TT ...
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... Synchronous DRAM Burst Write (single bank) @BL CLK /CS /RAS tRCD /CAS /WE CKE DQMU/L X A0-7 A10 X X A8,9,11 BA0 ACT#0 M5M4V64S40ATP-8A,-8L,-8, -10L, - tRC tRAS tRP tWR WRITE#0 PRE#0 MITSUBISHI ELECTRIC MITSUBISHI LSIs 10 11 ...
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... CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU/L A0 A10 X X A8,9, BA0 ACT#0 ACT#1 M5M4V64S40ATP-8A,-8L,-8, -10L, - tRC tRAS tWR WRITE#0 PRE#0 WRITE#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... CLK /CS /RAS tRCD /CAS /WE CKE DQMU/L A0-7 X A10 X A8,9,11 X BA0 ACT#0 M5M4V64S40ATP-8A,-8L,-8, -10L, - tRC tRAS tRP DQM read latency = CL READ#0 PRE#0 READ to PRE BL allows full data out Italic parameter indicates minimum case ...
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... CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU A0 A10 X X A8,9,11 BA0 ACT#0 ACT#1 M5M4V64S40ATP-8A,-8L,-8, -10L, - tRC tRAS DQM read latency = CL=3 CL READ#0 PRE#0 READ#1 Italic parameter indicates minimum case MITSUBISHI ELECTRIC ...
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... CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU/L A0 A10 X X A8,9, BA0 ACT#0 ACT#1 M5M4V64S40ATP-8A,-8L,-8, -10L, - tRC BL-1+ tWR + tRP WRITE#0 with AutoPrecharge WRITE#1 with AutoPrecharge MITSUBISHI ELECTRIC MITSUBISHI LSIs 10 11 ...
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... CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU A0 A10 X X A8,9,11 BA0 ACT#0 ACT#1 M5M4V64S40ATP-8A,-8L,-8, -10L, - tRC BL+tRP DQM read latency = CL=3 CL READ#0 with Auto-Precharge READ#1 with Auto-Precharge MITSUBISHI ELECTRIC MITSUBISHI LSIs 10 11 ...
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... Page Mode Burst Write (multi bank) @BL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU A0-7 A10 A8,9,11 BA0 ACT#0 ACT#1 M5M4V64S40ATP-8A,-8L,-8, -10L, - WRITE#0 WRITE#0 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... Page Mode Burst Read (multi bank) @BL=4 CL CLK /CS tRRD /RAS tRCD /CAS /WE CKE DQMU A0 A10 X X A8,9,11 BA0 ACT#0 ACT#1 M5M4V64S40ATP-8A,-8L,-8, -10L, - DQM read latency CL=3 CL READ#0 READ#0 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... CKE DQMU A0 A10 X X A8,9,11 BA0 ACT#0 WRITE#0 ACT#1 Burst Write can be interrupted by Write or Read of any active bank. M5M4V64S40ATP-8A,-8L,-8, -10L, - tCCD WRITE#0 WRITE#0 WRITE#1 MITSUBISHI ELECTRIC ...
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... CKE DQMU/L A0 A10 X X A8,9, BA0 ACT#0 ACT#1 Burst Read can be interrupted by Read or Write of any active bank. M5M4V64S40ATP-8A,-8L,-8, -10L, - DQM read latency READ#0 READ#0 READ#0 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... CKE DQMU A0 A10 X X A8,9,11 BA0 ACT#0 WRITE#0 ACT#1 Burst Write is not interrupted by Precharge of the other bank. M5M4V64S40ATP-8A,-8L,-8, -10L, - PRE#0 WRITE#1 MITSUBISHI ELECTRIC MITSUBISHI LSIs 10 11 ...
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... CKE DQMU A0 A10 X X A8,9,11 BA0 ACT#0 ACT#1 Burst Read is not interrupted by Precharge of the other bank. M5M4V64S40ATP-8A,-8L,-8, -10L, - DQM read latency READ#0 PRE#0 READ#1 MITSUBISHI ELECTRIC MITSUBISHI LSIs 10 ...
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... SDRAM (Rev.1.3) Mar'98 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Mode Register Setting CLK /CS /RAS /CAS /WE CKE DQMU/L A0-7 A10 A8,9,11 BA0,1 DQ Auto-Ref (last of 8 cycles) M5M4V64S40ATP-8A,-8L,-8, -10L, - tRC Mode Register Setting MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... CLK /CS /RAS /CAS /WE CKE DQMU/L A0-7 A10 A8,9,11 BA0,1 DQ Auto-Refresh Before Auto-Refresh, all banks must be idle state. M5M4V64S40ATP-8A,-8L,-8, -10L, - tRC ACT#0 After tRC from Auto-Refresh, all banks are idle state. MITSUBISHI ELECTRIC MITSUBISHI LSIs 11 12 ...
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... CKE CKE must be low to maintain Self-Refresh DQMU/L A0-7 A10 A8,9,11 BA0,1 DQ Self-Refresh Entry Before Self-Refresh Entry, all banks must be idle state. M5M4V64S40ATP-8A,-8L,-8, -10L, - CLK can be stopped tSRX Self-Refresh Exit After tRC from Self-Refresh Exit, all banks are idle state. ...
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... Mar'98 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM DQM Write Mask @BL CLK /CS /RAS tRCD /CAS /WE CKE DQMU/L A0-7 X A10 X A8,9,11 X BA0 ACT#0 M5M4V64S40ATP-8A,-8L,-8, -10L, - masked WRITE#0 WRITE#0 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... Synchronous DRAM DQM Read Mask @BL=4 CL CLK /CS /RAS tRCD /CAS /WE CKE DQMU/L X A0-7 X A10 X A8,9,11 BA0 ACT#0 M5M4V64S40ATP-8A,-8L,-8, -10L, - DQM read latency READ#0 READ#0 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... SDRAM (Rev.1.3) Mar'98 64M (4-BANK x 1048576-WORD x 16-BIT) Synchronous DRAM Power Down CLK /CS /RAS /CAS /WE CKE DQMU/L A0-7 A10 A8,9,11 BA0,1 DQ Precharge All M5M4V64S40ATP-8A,-8L,-8, -10L, - Standby Power Down CKE latency ACT#0 MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... Synchronous DRAM CLK Suspend @BL=4 CL CLK /CS /RAS tRCD /CAS /WE CKE CKE latency=1 DQMU/L X A0-7 X A10 X A8,9,11 BA0 ACT#0 M5M4V64S40ATP-8A,-8L,-8, -10L, - CKE latency WRITE#0 READ#0 CLK suspended MITSUBISHI ELECTRIC MITSUBISHI LSIs ...
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... Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 7.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein. M5M4V64S40ATP-8A,-8L,-8, -10L, -10 MITSUBISHI ELECTRIC MITSUBISHI LSIs 51 ...